Gate-oxide breakdown under RF stress:
experiments, analysis, and effect on circuit operation
D. Sanzogni1, L. Larcher2, R. Brama2, A. Mazzanti2, F. Svelto1
1Università
di Pavia
2Università di Modena e Reggio Emilia
Riunione Annuale GE 2006
Ischia, 21-23 giugno 2006
Introduction

Limits of literature papers: BD and Hot
Carrier (HC) effects on devices and
circuits (Low Noise Amplifier and Mixer)
studied only after DC stresses.

Need for oxide lifetime investigation and
new BD limits at RF.
Riunione Annuale GE 2006
Ischia, 21-23 giugno 2006
High Efficiency Power Amplifiers
The peak VDS
voltage is divided
between the two
devices
Riunione Annuale GE 2006
VG=1.28 VDD+VT
Vin=±VDD
VDG1,MAX=VDG2,MAX=2.28VDD-VT
Ischia, 21-23 giugno 2006
Experimental Results: POUT
26
POUT [dBm]
25
24
23
22
4V
4.5V
5V
21
freq = 1.8GHz
20
1.E+00
1.E+02
1.E+04
1.E+06
Time [s]
Voltage accelerated stress Vdd = 4, 4.5 and 5V.
Riunione Annuale GE 2006
Ischia, 21-23 giugno 2006
Equivalent Model
VDD

LC

Cout L1+Lmatch
VCASC
RDD
RGG
M2
RSS
Bias
PA

[1] Y.-S. Yeoh, et al. Proc. IEEE
33rd IRPS, pp. 149-155, 1995.
LS
M1
IN
OUT
Ca
Broken MOS fingers modeled through resistors [1]
RGG accounts for doping
diffusion through broken
oxide;
RSS & RDD account for
broken n-well to S/D.
VDD [V] VDG,MAX [V]
RGG []
RDD [] RSS []
4
10.4
1500
1
5
4.5
11.3
700
1
5
5
12.1
500
1
5
Riunione Annuale GE 2006
Ischia, 21-23 giugno 2006
Estimated Time to Breakdown
1.E+09
10 YEARS
1.E+08
TDDB [s]
1.E+07
1.E+06
1.E+05
1.E+04
1.E+03
DC
@ 80 MHz
@ 1.8 GHz
1.E+02
1.E+01
1.E+00
4
6
8
10
12
ERMS [MV/cm]
Higher voltage peaks can be tolerated @ RF.
Riunione Annuale GE 2006
Ischia, 21-23 giugno 2006
Conclusions

Voltage DC breakdown limits are too conservative
when the stress is at RF

Oxide degradation due to RF stress is explained
and modeled by considering the RMS value of the
oxide field as the stress triggering parameter

Higher voltage peaks can be tolerated leading to
new design perspectives in CMOS RF circuits

BD effects on class-E PA operation could be
tolerated using proper circuit topologies
Riunione Annuale GE 2006
Ischia, 21-23 giugno 2006