TMS320C6000
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Instruction Set
'C6xx Instruction Set - Operands
ADD .L1
A0, A1, A2
ADD .L2
-5, B3, B4
ADD .L1
A2, A3, A5:A4
ADD .L1
A2, A5:A4, A5:A4
ADD .L2
3, B9:B8, B9:B8
2
'C6xx Instruction Set - Cross Path
ADD
MPY
SUB
ADD
.L2x
.M1x
.S1x
.L1x
A0,A1,B2
A0,B6,A9
A8,B2,A8
A0,B0,A2
LDW .D1T2 *A0,B5
STW .D2T1 A5,*B0
3
'C6xx Instruction Set
Parallel Operation
L1
S1
ADD .L2x
| | MPY .M1x
SUB .S1x
ADD .L1x
M1
A0,A1,B2
A0,B6,A9
A8,B2,A8
A0,B0,A2
D1
L2
S2
M2
D2
LDW .D1T2 *A0,B5
|| STW .D2T1 A5,*B0
4
'C62x Instruction Set (by category)
Arithmetic
Logical
Data Mgmt
AND
ABS
LDB/H/W
Aritmetica
di
saturazione
Two
16-Bit
Integer
Adds
on
CMPEQ
(=)
ADD
Integer
Addition
MV
Se utilizzo
la CMPGT
classica
aritmetica
di arrotondamento
quando,
(>)
ADDA
Upper
and
Lower
Register
Halves
Integer
Addition
MVC
Addressin
Mode
CMPLT
(<)
ADDK
adUsing
esempio
in un procedimento
di incremento
di colore,
MVK
Using SignedNOT
16-Bit
Constant
if rappresentazione
(cond)
ADD2
giungo or
al limite
di
di
un dato un ulteriore
Signed
Unsigned
Integer
Multiply
MVKL
OR
MPY
{((lsb16(src1)
+determina
lsb16(src2))
and
FFFFh)
or il numero che
Signed
or16
Unsigned
Integer
Multiply
MVKH
incremento
un
overflow
con
x 16 lsb<< 16) ->MVKLH
(<<)
MPYH
((msb16(src1)SHL
+lsb
msb16(src2))
dst}
raggiunge
erroneamente
il
limite
opposto.
16
msb
x
16
msb
SHR
(>>)
NEG
else nop
STB/H/W
Quando io sommo
SSHLinvece ad esempio due valori a 32 bit che
SMPY
XOR un valore che eccede i limiti di
SMPYH
raggiungono
SADD
Program bisogno
Ctrl di
rappresentazione avrei semplicemente
SAT
B
Bit che
Mgmt
indicare
ho raggiunto
il valore
massimo
SSUB
Conditional
Integer
Subtract
and
IDLE Shift
rappresentabile.
particolarmente
SUB
CLR Questo è un evento
NOP
Used
for Division
SUBA
frequente inEXT
applicazioni multimediali (ad esempio nei
SUBC
if (cond)
valori di coloreLMBD
dei pixel)
e l’aritmetica di saturazione serve
SUB2
NORM
{if (src1 – src2 >= 0) ( (src1–src2) << 1) + 1 -> dst
appunto a questo.
ZERO
SET
else src1 << 1 -> dst}
5
else Guide
nop for more details.
Note: Refer to the 'C6000 CPU Reference
'C62x Instruction Set (by unit)
.L Unit
.S Unit
ADD
ADDK
ADD2
AND
B
CLR
EXT
MV
MVC
MVK
MVKL
MVKH
MVKLH
NEG
NOT
OR
SET
SHL
SHR
SSHL
SUB
SUB2
XOR
ZERO
ABS
ADD
AND
CMPEQ
CMPGT
CMPLT
LMBD
MV
NEG
NORM
NOT
OR
SADD
SAT
SSUB
SUB
SUBC
XOR
ZERO
TMS320C62x/C64x/C67x
Fixed-Point Instruction Set
.M Unit
MPY
MPYH
SMPY
SMPYH
Other
NOP
.D Unit
ADD
ADDA
LDB/H/W
MV
NEG
STB/H/W
SUB
SUBA
ZERO
6
IDLE
Note: Refer to the 'C6000 CPU
Reference Guide for more details.
' C67x: Superset of Floating-Point
(by unit)
.S Unit
ADD
ADDK
ADD2
AND
B
CLR
EXT
MV
MVC
MVK
MVKL
MVKH
NEG
NOT
OR
SET
SHL
SHR
SSHL
SUB
SUB2
XOR
ZERO
ABSSP
ABSDP
CMPGTSP
CMPEQSP
CMPLTSP
CMPGTDP
CMPEQDP
CMPLTDP
RCPSP
RCPDP
RSQRSP
RSQRDP
SPDP
.L Unit
ABS
ADD
AND
CMPEQ
CMPGT
CMPLT
LMBD
MV
NEG
NORM
NOT
OR
SADD
SAT
SSUB
SUB
SUBC
XOR
ZERO
ADDSP
ADDDP
SUBSP
SUBDP
INTSP
INTDP
SPINT
DPINT
SPTRUNC
DPTRUNC
DPSP
.M Unit
MPY
SMPY
MPYSP
32-Bit Integer Multiply
.D Unit– Result Is Lower 32 Bits
MPYH
MPYLH
MPYHL
32-Bit
SMPYH
MPYDP
MPYI
MPYID
ADD
NEG
ADDAB (B/H/W) STB
(B/H/W)
ADDAD
SUB
Used
LDB Multiply
(B/H/W) SUBAB
(B/H/W) Is LowerNo
Integer
– Result
64Unit
Bits
7
NOP
IDLE
LDDW
ZERO
MV
Note: Refer to the 'C6000 CPU Reference Guide for more details.
Superset of Floating-Point
Control Registers
Instruction Dispatch
Advanced Instruction
Packing
Instruction Decode
Emulation
L1
+
+
+
+
Interrupt
Control
Instruction Fetch
Advanced
Emulation
Registers (A0 - A15)
Registers (B0 - B15)
Registers (A16 - A31)
Registers (B16 - B31)
S1
+
+
+
+
M1
x
x
x
x
X
D1
+
+
X
D2
+
M2
X
+
X
x
x
x
x
S2
+
+
+
+
L2
+
+
+
+
‘C62x: Dual 32-Bit Load/Store
8
‘C64x: Dual 64-Bit Load/Store
‘C67x: Dual 64-Bit Load/32-Bit Store
'C64x: Superset Fixed-Point of ‘C62x
.S
.D
Dual/Quad Arith
SADD2
SADDUS2
SADD4
Data Pack/Un
PACK2
PACKH2
PACKLH2
PACKHL2
Bitwise Logical UNPKHU4
ANDN
UNPKLU4
Shifts & Merge SWAP2
SPACK2
SHR2
SPACKU4
SHRU2
SHLMB
SHRMB
Dual Arithmetic Mem Access
ADD2
LDDW
SUB2
LDNW
LDNDW
Bitwise Logical STDW
AND
STNW
ANDN
STNDW
OR
XOR
Load Constant
MVK (5-bit)
Address Calc.
ADDAD
Compares
CMPEQ2
CMPEQ4
CMPGT2
CMPGT4
.L
Branches/PC
BDEC
BPOS
BNOP
ADDKPC
Dual/Quad Arith
ABS2
ADD2
ADD4
MAX
MIN
SUB2
SUB4
SUBABS4
Bitwise Logical
ANDN
.M
Average
AVG2
AVG4
Shifts
ROTL
SSHVL
SSHVR
Data Pack/Un
PACK2
PACKH2
PACKLH2
PACKHL2
PACKH4
PACKL4
UNPKHU4
UNPKLU4
SWAP2/4
Multiplies
MPYHI
Shift & Merge
MPYLI
SHLMB
MPYHIR
SHRMB
MPYLIR
Load Constant
MPY2
MVK (5-bit)
SMPY2
Bit Operations DOTP2
DOTPN2
BITC4
DOTPRSU2
BITR
DOTPNRSU2
DEAL
DOTPU4
SHFL
DOTPSU4
9
Move
GMPY4
MVD
XPND2/4
TMS320C6000
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
Architecture
'C6x - System Block Diagram
Memory
External
Memory
Internal Buses
.M1 .M2
.L1 .L2
.S1 .S2
Control Regs
CPU
Regs (B0-B15)
Regs (A0-A15)
.D1 .D2
P
E
R
I
P
H
E
R
A
L
S
11
‘C6x - Internal Buses
VLIW
Read
Write
‘C67x
can perform 64-bit data loads.
12
'C6x - System Block Diagram
13
'C6x - System Block Diagram
512
32/64
32/64
32/64
32/64
32/64
14
'C6x - Peripherals
15
EMIF
16
Memory size per device
LINK: TMS320C6000 DSP Generation
Devices
Internal
C6201, C6701
C6204, C6205
P =
D=
64 kB
64 kB
C6202
P=
D=
256 kB
128 kB
C6203
P=
D=
C6211
C6711
C6712
L1P =
L1D =
L2 =
C6713
L1P =
L1D =
L2 =
C6411
DM642
L1P =
L1D =
L2 =
C6414
C6415
C6416
L1P =
L1D =
L2 =
EMIF A
52M Bytes
(32-bits wide)
EMIF B
N/A
384 kB
512 kB
4 kB
4 kB
64 kB
4 kB
4 kB
256 kB
128M Bytes
(32-bits wide)
N/A
64M Bytes
(16-bits wide)
128M Bytes
(32 - bits wide)
N/A
16 kB
16 kB
256 kB
128M Bytes
(32-bits wide)
N/A
16 kB
16 kB
1 MB
256M Bytes
(64-bits wide)
64M Bytes
(16-bits17
wide)
HPI / XBUS / PCI
18
GPIO
19
McBSP/ASP and Utopia
20
DMA / EDMA
21
Timer / Counter
22
Ethernet
23
Video Ports
24
VCP / TCP - 3G Wireless
25
Phase Locked Loop (PLL)
26
Clock Cycle
27
C6713 Architecture
28
C6713-DSK Architecture
29
C6416
Architecture
30
C6416-DSK Architecture
31
‘C6x - Family Part Numbering
Ex = TMS320 L C6 2 01 PKG A 200








TMS320
L
C6
2
01
PKG
A
200
=
=
=
=
=
=
=
=
TI DSP
Place holder for voltage levels
C6x family
Fixed-point core
Memory/peripheral configuration
Pkg designator (actual letters TBD)
-40 to 85C (blank for 0 to 70C)
Core CPU speed in Mhz
32
Architecture

Links:





C6711 data sheet: tms320c6711.pdf
C6713 data sheet: tms320c6713.pdf
C6416 data sheet: tms320c6416.pdf
User guide C6xx: spru189f.pdf
Errata: sprz173c.pdf
33