TMS320
TMS320C6xx
C6xx
Instruction Set
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
'C6xx Instruction Set - Operands
ADD .L1
A0, A1, A2
ADD .L2
-5, B3, B4
ADD .L1
A2, A3, A5:A4
ADD .L1
A2, A5:A4, A5:A4
ADD .L2
3, B9:B8, B9:B8
2
'C6xx Instruction Set - Cross Path
TMS320
ADD
MPY
SUB
ADD
.L2x
.M1x
.S1x
.L1x
C67x
A0,A1,B2
A0,B6,A9
A8,B2,A8
A0,B0,A2
LDW .D1T2 *A0,B5
STW .D2T1 A5,*B0
3
'C6xx Instruction Set
Parallel Operation
L1
S1
ADD .L2x
| | MPY .M1x
SUB .S1x
ADD .L1x
M1
A0,A1,B2
A0,B6,A9
A8,B2,A8
A0,B0,A2
D1
L2
S2
M2
D2
LDW .D1T2 *A0,B5
|| STW .D2T1 A5,*B0
4
TMS320
TMS320C6xx
C62x
Instruction Set
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
'C62x Instruction Set (by category)
Arithmetic
Logical
Data Mgmt
AND
Aritmetica
di saturazione
LDB/H/W
Two 16-Bit
Integer
CMPEQ
(=) Adds on
ABS
ADD
Integer
Addition
MV
Se utilizzo
laCMPGT
classica(>)
aritmetica di arrotondamento
in un
ADDA
Upper
and
Lower
Register
Halves
Integer
Addition
MVC
Using
Addressing
Mode di colore
procedimento
di incremento
allora se dovessi
CMPLT
(<)
ADDK
MVK
Using Signed
16-Bit
Constant
if
NOT
ADD2
giungere
al Unsigned
limite
di(cond)
rappresentazione
di un dato un ulteriore
Signed
or
Integer
Multiply
MVKL
OR
MPY
{((lsb16(src1)
+determinerebbe
lsb16(src2))
and FFFFh)
or
Signed
or16
Unsigned
Integer
Multiply
incremento
un
overflow
(il numero
MVKH
lsb
x
16
lsb
SHL
(<<)
MPYH
((msb16(src1)
+ msb16(src2))
<< 16) ->
dst}
MVKLH
raggiungerebbe
erroneamente
il
limite opposto).
16
msb
x
16
msb
SHR
(>>)
NEG
else nop
STB/H/W
Quando io sommo
SSHLinvece ad esempio due valori a 32 bit che
SMPY
XOR un valore che eccede i limiti di
SMPYH
raggiungono
SADD
Program
Ctrl
rappresentazione, in un procedimento
di incremento
di
SAT
B di indicare che ho
Bitsemplicemente
Mgmt
colore, avrei
bisogno
SSUB
Conditional
Integer Subtract
and Shift
IDLE
SUB
CLR massimo rappresentabile.
raggiunto il valore
Questo è un
NOP
Used
for
Division
SUBA
EXT
evento particolarmente
frequente in applicazioni
SUBC
LMBD if (cond)
multimediali
(ad esempio nei valori di colore dei pixel) e
SUB2
NORM
{if (src1 – src2
>= 0) ( (src1–src2) << 1) + 1 -> dst
l’aritmetica
di saturazione serve appunto a questo.
ZERO
SET
else src1 << 1 -> dst}
6
else Guide
nop for more details.
Note: Refer to the 'C6000 CPU Reference
'C62x Instruction Set (by unit)
.L Unit
.S Unit
ADD
ADDK
ADD2
AND
B
CLR
EXT
MV
MVC
MVK
MVKL
MVKH
MVKLH
NEG
NOT
OR
SET
SHL
SHR
SSHL
SUB
SUB2
XOR
ZERO
ABS
ADD
AND
CMPEQ
CMPGT
CMPLT
LMBD
MV
NEG
NORM
NOT
OR
SADD
SAT
SSUB
SUB
SUBC
XOR
ZERO
TMS320C62x/C64x/C67x
Fixed-Point Instruction Set
.M Unit
MPY
MPYH
SMPY
SMPYH
Other
NOP
.D Unit
ADD
ADDA
LDB/H/W
MV
NEG
STB/H/W
SUB
SUBA
ZERO
7
IDLE
Note: Refer to the 'C6000 CPU
Reference Guide for more details.
TMS320
TMS320C6xx
C67x
Instruction Set
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
' C67x: Superset of Floating-Point
(by unit)
.S Unit
ADD
ADDK
ADD2
AND
B
CLR
EXT
MV
MVC
MVK
MVKL
MVKH
NEG
NOT
OR
SET
SHL
SHR
SSHL
SUB
SUB2
XOR
ZERO
ABSSP
ABSDP
CMPGTSP
CMPEQSP
CMPLTSP
CMPGTDP
CMPEQDP
CMPLTDP
RCPSP
RCPDP
RSQRSP
RSQRDP
SPDP
.L Unit
ABS
ADD
AND
CMPEQ
CMPGT
CMPLT
LMBD
MV
NEG
NORM
NOT
OR
SADD
SAT
SSUB
SUB
SUBC
XOR
ZERO
ADDSP
ADDDP
SUBSP
SUBDP
INTSP
INTDP
SPINT
DPINT
SPTRUNC
DPTRUNC
DPSP
.M Unit
MPY
SMPY
MPYSP
32-Bit Integer Multiply
.D Unit– Result Is Lower 32 Bits
MPYH
MPYLH
MPYHL
32-Bit
SMPYH
MPYDP
MPYI
MPYID
ADD
NEG
ADDAB (B/H/W) STB
(B/H/W)
ADDAD
SUB
Used
LDB Multiply
(B/H/W) SUBAB
(B/H/W) Is LowerNo
Integer
– Result
64Unit
Bits
9
NOP
IDLE
LDDW
ZERO
MV
Note: Refer to the 'C6000 CPU Reference Guide for more details.
Superset of Floating-Point
Control Registers
Instruction Dispatch
Advanced Instruction
Packing
Instruction Decode
Emulation
L1
+
+
+
+
Interrupt
Control
Instruction Fetch
Advanced
Emulation
Registers (A0 - A15)
Registers (B0 - B15)
Registers (A16 - A31)
Registers (B16 - B31)
S1
+
+
+
+
M1
x
x
x
x
X
D1
+
+
X
D2
+
M2
X
+
X
x
x
x
x
S2
+
+
+
+
L2
+
+
+
+
‘C62x: Dual 32-Bit Load/Store 10
‘C64x: Dual 64-Bit Load/Store
‘C67x: Dual 64-Bit Load/32-Bit Store
TMS320
TMS320C6xx
C64x
Instruction Set
Dr. Naim Dahnoun, Bristol University, (c) Texas Instruments 2004
'C64x: Superset Fixed-Point of ‘C62x
.S
.D
Dual/Quad Arith
SADD2
SADDUS2
SADD4
Data Pack/Un
PACK2
PACKH2
PACKLH2
PACKHL2
Bitwise Logical UNPKHU4
ANDN
UNPKLU4
Shifts & Merge SWAP2
SPACK2
SHR2
SPACKU4
SHRU2
SHLMB
SHRMB
Dual Arithmetic Mem Access
ADD2
LDDW
SUB2
LDNW
LDNDW
Bitwise Logical STDW
AND
STNW
ANDN
STNDW
OR
XOR
Load Constant
MVK (5-bit)
Address Calc.
ADDAD
Compares
CMPEQ2
CMPEQ4
CMPGT2
CMPGT4
.L
Branches/PC
BDEC
BPOS
BNOP
ADDKPC
Dual/Quad Arith
ABS2
ADD2
ADD4
MAX
MIN
SUB2
SUB4
SUBABS4
Bitwise Logical
ANDN
.M
Average
AVG2
AVG4
Shifts
ROTL
SSHVL
SSHVR
Data Pack/Un
PACK2
PACKH2
PACKLH2
PACKHL2
PACKH4
PACKL4
UNPKHU4
UNPKLU4
SWAP2/4
Multiplies
MPYHI
Shift & Merge
MPYLI
SHLMB
MPYHIR
SHRMB
MPYLIR
Load Constant
MPY2
MVK (5-bit)
SMPY2
Bit Operations DOTP2
DOTPN2
BITC4
DOTPRSU2
BITR
DOTPNRSU2
DEAL
DOTPU4
SHFL
DOTPSU4
12
Move
GMPY4
MVD
XPND2/4