1st ERDIAP Workshop
Como, Italy
February 23, 2011
Program committee:
Edith Beigne,
CEA-LETI, Grenoble, France
Giovanni Beltrame
École Polytechnique de
Montréal, Canada
Cristiana Bolchini
Politecnico di Milano, Italy
Philippe Bonnot
THALES, France
Paulo F. Butzen
FURG, Rio Grande, Brazil
Andrea Calimera
Politecnico di Torino, Italy
Philippe Coussy
Univ. de Bretagne-Sud, France
Giuseppe Desoli
STMicroelectronics, Italy
Petr Dobrovolny
IMEC, Belgium
Martin Elhøj
Nangate, Denmark
Fabrizio Ferrandi
Politecnico di Milano, Italy
Arnaud Grasset
THALES, France
Elio Guidetti
STMicroelectronics, Italy
Igor Markov
Univ. of Michigan, USA
Felipe Marques
UFPEL, Pelotas, Brazil
David Merodio Codinachs
ESA, Netherlands
Miguel Miranda Corbalan
IMEC, Belgium
Francesc Moll Echeto
UPC, Spain
Davide Pandini
STMicroelectronics, Italy
Christian Pilato
Politecnico di Milano, Italy
André I. Reis
UFRGS, Porto Alegre, Brazil
Renato P. Ribas
UFRGS, Porto Alegre, Brazil
Leomar Rosa Jr
UFP, Pelotas, Brazil
Sachin S. Sapatnekar
Univ. of Minnesota, USA
Donatella Sciuto
Politecnico di Milano, Italy
Tiziano Villa
Univ. of Verona, Italy
Stephan Wong
TU Delft, Netherlands
Nigel Woolaway
Leading Edge, Italy
Exploiting Regularity in the Design of IPs, Architectures and
Platforms
http://conferences.dei.polimi.it/erdiap2011
Call for Papers
With the introduction of advanced process nodes, new and significant layout restrictions
lead to a more regular layout style. The workshop targets the optimization of
manufacturability and the reduction of systematic variations in nanometer technologies
through exploitation of regularity at the architectural, structural, and geometrical levels.
This workshop will have three main sessions:
1.Regular architectures and applications. This session is devoted to exploit regularity at
the level of architecture and applications, including consequences at lower levels.
2.Regular design methodologies. This session is targeted to exploit regularity at the
structural logic level. The emphasis is given to the implications of regularity in design
methodologies, including methods for logic synthesis targeting regularity and automatic
regularity extraction at the structural logic level.
3.Layout and Memory Design & Characterization under Regularity Constraints. This
session aims to discuss regularity at the layout level, including the physical design to
produce regular layouts as well as characterization of the effects imposed by regularity.
The ERDIAP workshop is connected with the SYNAPTIC FP7 project (http://www.synapticproject.eu) and it will be held on February 23rd, 2011 in conjunction with ARCS 2011,
Como, Italy (http://conferences.dei.polimi.it/arcs2011).
Important Dates:
• Paper submission deadline: December 15, 2010 EXTENDED: December 20, 2010
• Acceptance notification: January 6, 2011
• Camera-ready paper due: January 10, 2011
• Workshop: February 23, 2011
Submission guidelines: Authors are invited to submit original, unpublished paper.
Previously published papers or papers currently under review for other conferences or
journals should not be submitted and will not be considered. Electronic submission in PDF
format should be done through the workshop website. Authors should indicate the track in
which they would like to present their contribution in first page of the manuscript.
Paper format: Submissions must not exceed 10 pages and should be formatted according
to VDE-Verlag style (http://www.vde-verlag.de/proceedings-en/type-instructions.html).
Presentation form: Accepted papers will be chosen for a full oral presentation (20-25 min.)
Contacts: for further information, please send an email to [email protected].
Organizing committee
General chairs:
Giuseppe Desoli
STMicroelectronics, Italy
Fabrizio Ferrandi
Politecnico di Milano, Italy
Program chairs:
André Reis
Fed. Univ. of Rio Grande do Sul, Brazil
Francesc Moll Echeto
Univ. Politècnica de Catalunya, Spain
Publicity chair:
Christian Pilato
Politecnico di Milano, Italy
Publication chair:
Antonio Miele
Politecnico di Milano, Italy