Muon System Electronics Upgrade
Meeting Summary
Alessandro Cardini / INFN Cagliari
Roma, October 10, 2014
A. Cardini / INFN Cagliari
2
nSYNC Architecture
TDC + Histogram builder:
• 4 bit TDC (1.5 ns resolution @ 40 MHz)
• 16 bins of 224 entries each. The counts stop when any of the bins
saturates. Dead time free in hit capture.
Muon Trigger TELL40 Interface:
• Sends synchronized hits every machine cycle (40 MHz).
• Prog. buffer depth to guarantee the synchronization between
different nSYNC sending data through the same GBT
TDC ZS:
• Zero Suppression of TDC’s data not related to hit events.
TDC TELL40 Interface:
• Sends synchronized ZS TDC data every machine cycle (40 MHz).
• Prog. buffer depth to guarantee the synchronization between
different nSYNC sending data through the same GBT
I2C Interface:
• Configure through the ECS.
• Triple-voted configuration
S. Cadeddu - INFN Cagliari
Roma - 08/10/14
3
nSYNC: alcuni punti (quasi) fermi
• Tecnologia:
– Al momento UMC 130 nm
– In attesa di notizie/decisioni dal CERN sulla TSMC 130 nm
• 48 canali
– 1 GBT per nSYNC => 4 link indipendenti per nODE
– 1 GBT_TFC per nODE
– 1 GBT_SCA per nODE
• Clock
– 40 MHz di sistema (da dove?)
– 80/160/320 MHz per interfacce GBT (quale frequenza?; Il clock generato dal
GBT stesso?)
• Interfaccia ECS
– I2C o SPI (?)
S. Cadeddu - INFN Cagliari
Roma - 08/10/14
4
• 1 GBTx forTFC/ECS
GBTx
VTTx
– MasterGBT
GBTx
• 1 GBT-SCA
• 2 VTTx
• 1 VTRx
VTRx
GBTx
ECS
GBT
SCA
nSYNC
nSYNC
nSYNC
8/10/2014
Paolo Ciambrone INFN- LNF
– 12 out of 48 channels (25%
occupancy)
– Truncation event by event
TDC out Trig hit TDC out Trig hit
GBTx
48Input ch
• 16 bits for header
• 48 bits for data hits
• 48 bits for TDC data
48Input ch
VTTx
nSYNC
48Input ch
GBTx
• 4 GBTx for hit+ TDC data
– Slave GBT
– Widebus 112 bits
TDC out Trig hit TDC out Trig hit
• nSYNC @ 48 channels
48Input ch
nODE NOW
• Livelli logici usati
– SLVS e CMOS
8/10/2014
GBTx clock
• Input clock
– Power-up
• Ha bisogno di un reference clock per effettuare la procedura di startup del chip e
di inizializzazione del link
• 3 opzioni
Low-jitter external clock
 opzione consigliate per i GBT slave
External clock+internal XPLL
 opzione consigliate per i GBT slave
Internal XPLL in XOSC mode (usa un quarzo incapsulato nel package)  opzione
consigliate per i GBT master
• La scelta viene effettuata tramite un pin esterno tra opt. 1 e 2/3 e con un registro
interno tra opt.2 e 3
• Alla fine della procedure di power-on ( 2ms) vengono generati dei segnali di ready
– rxRdy (receiver ready): the receiver part of the GBTX is ready for operation
– txRdy (transmitter ready): the transmitter part of the GBTX is ready for operation
– Dopo l’init del link ottico il clock del GBTx è sincrono con:
• il clock estratto dai dati del link ottico se il GBTx lavora in modalità duplex
• il reference clock se il GBTx lavora in modalità Simplex-TX
Paolo Ciambrone INFN- LNF
1.
2.
3.
• Occorre scegliere uno schema che
– Garantisca la massima flessibilità
– Minimizzi il numero di input verso l’nSYNC
8/10/2014
GBTx clock
Paolo Ciambrone INFN- LNF
– Nota: bisogna capire se/come sincronizzare il clock con i comandi del TFC
•
•
4 bit Header (H) field (2 types)
2 bit Internal Control (IC) field used to control and monitor the GBTX operation
•
2 bit External Control (EC) field to implement a slow control channel (e.g. for the GBT-SCA)
•
112 bit Data (D) field for generic transmission of data
–
Its use is strictly reserved for the GBTX control.
–
its use is not restricted to this application and can be used for generic data transmission applications.
8/10/2014
Paolo Ciambrone INFN- LNF
GBTx wide frame format
8/10/2014
• Recommended communication links within a FE module
Paolo Ciambrone INFN- LNF
TFC+ECS
8/10/2014
• List of mandatory monitoring counters in an FE module
Paolo Ciambrone INFN- LNF
ECS interface
PCIe40 Firmware
• In Rome2 the PCIe40 firmware development environment is
ready
• Minidaq boad expected by the end of the month – currently
under test in Marseille
• Then:
– start Minidaq standalone testing
– Useful environment to start developing new ECS software (M.
Carletti)
– Will purchase few GBT test board (with VTTRx, GBT & GBT-SCA)
MiniDaq
Roma, October 10, 2014
MiniDaq
A. Cardini / INFN Cagliari
GBT test b.
11
New Service Board Module
(multiple GBT old Backplane)
Long line I2C
FE converter
E-Link
80 Mbits/s
Flash
FPGA
GBT-SCA
I2C
CLK40
BC Pulse
test
pulse
logic
IGLOO2
Actel
Flash
FPGA
12 x I2C
lines
SCL
SDA_IN
SDA_OUT
Test/Pulse
RESET
1
2
Test/pulse
Long line I2C
FE converter
Test/pulse
Long line I2C
FE converter
Test/pulse
Long line I2C
FE converter
3
1
2
3
1
2
3
1
2
Test/pulse
3x
LVDS I2c
each ELMB
3
ttl/lvds
converter
Valerio Bocci 2014
New Pulse Distribution Module
single GBT
GBT
Fiber
16 x
E-Link
80Mbits/s
GBT
I2C
BC
counter
BC
Pulse
Generator
IGLOO2
Actel
Flash
FPGA
40 MHz
Machine
CLK
2 LVDS
2 LVDS
Sync
BC
pulse
Valerio Bocci 2014
New Custom Backplane
80 Mbits/s E-LINK
P
D
M
S
L
O
T
New Custom Backplane routing 80 Mbits/s E-Link Lines
And Service line
Valerio Bocci 2014
LVDS Test of the new IGLOO2 Flash FPGA
Cardiacs
Patch bypass lvds
LVDS Test using IGLOO2
bypassing SB
SB
EB Igloo2
LVDS
• Service Board
• IGLOO2 Evaluation Board
• Microcontroller Board to drive standard I2C
Valerio Bocci 2014
Removing HW Muon LLT option
• The final design of the nSYNC ASIC and of the nODE board
depend also on how we are planning to implement the
Muon LLT
• A SW-only muon LLT will allow an hardware simplification
and an important money saving (fewer pins on the nSYNC,
fewer optical link on the nODE) because we could
remove the output lines to the LLT
• In addition, further changes to the current muon system
layout are only possible in the case of a full software LLT
• Discussions have already started during an electronics
upgrade meeting on June 27th, 2014; there are no
opposition in principle (SW LLT is already the baseline)
• In Orsay we decided to approve this choice at next TB in
December. A documents describing
advantages/disadvantages will be prepared together
with Julien C.
Orsay, 16/09/2014
A. Cardini / INFN Cagliari
16