SVT upgrade
AM 32kpat  128kpat
• SVT upgrade:
Road Warrior
a) E’ parte dei DAQ upgrades per
aumentare “Trigger bandwidths”
b) Tracce SVX only per migliorare il
trigger di leptone inclusivo
• DAQ upgrades a CDF: 6 M$
• Chi saremo – Schedule
Paola Giannetti – Gruppo I Lecce - 24 settembre 2003
SVT: Silicon Vertex Trigger
XFT + SVX 4/4
6/2003)
(fino a
XFT + SVX 4/5, more
efficient
Instead of XFT:

XFT tracks
SVX hits
m 1<h<1.5
e 1<h<2.5
New Functionalities:
m + SVX 4/5, 1< h< 1.5
e + SVX 4/5, 1< h< 2.5
I limiti ai rate dei tre livelli di trigger
XFT (2227 k$)
L2 (429 k$)
SRC (Done)
SVT (? K$)
350 Hz (L3-EVB)
15 kHz (L2 proc. Time)
TDC (2132 k$)
EVB (680 k$)
L3 (631 k$)
upgrade
L1 Accept rate (Hz)
L2 Accept rate (Hz)
upgrade
Time (sec)
Dead Time
CSL (?k$)
Offline (1M$)
upgrade
70-80 Hz (L3-CSL)
L3 Accept rate
5%
Time (sec)
DeadTime
Accurate deadtime model (ModSim) to
M. Schmidt
1. Two SRCs in parallel
understand DAQ upgrades
2. L2 processor upgrade
3.
4.
5.
4/4
87 bit SVX digit.
-3 ms in SVT proc.time
cut SVT tails above 27
msec
20 kHz
5%
4/4 – 4/5
35 kHz
25 kHz
1.
2.
3.
L1A rate (kHz)
BUT the recent
use of 4/5 in SVT
changes the conditions!
match piu’ debole
Ghost roads
5 layers: Pattern + larghi
4/4 – 4/5
27 msec
Time (ms)
WHY 4/5?
Signal Yields with 4/5
D0
1430
4/5
J/psi
D0
970
4/4
Marco Rescigno CSL review 6/23/03
Signal Yields in 4/5
Several studies:
• D0 peaks in RUN 164303 (4/4) and
164304 (4/5) (Rolf)
• EXPRESS_JPSI stream for 4/5
runs with svtsim emulation of 4/4
to get directly the yield increase of
J/psi with both legs an SVT track
• BGEN MC with realistic
simulation of BsDsp(fp) p
• Increase in signal yield
match almost exactly the
increase in L3 yield:
S/B unchanged
GAIN
50-60 %
source
4/4
D0 yield
11.2 (nb)
17.5
(nb)
1.55
±0.06
663
974
1.5
J/psi yield
Bs MC
(Pt_b>5.5;
|h_b|<1.3)
Bs MC after
offline
reconstructi
on (Ivan F.)
4/5
R
1.59
±0.05
1.58
Marco Rescigno CSL review 6/23/03
Tempi di processamento: come agisce l’upgrade ?
raw data from
SVX front end
NUOVA AM piu’ grande
Hit Finders
Sequencer
Associative Memory
COT tracks
fromXTRP
roads
x 12 phi sectors
Road Warrior
12 fibers
hits
Track Fitter
Merger
hits
to Level 2
Hit Buffer
Ricetta per velocizzare il tempo di esecuzione di SVT:
1.
pattern piu’ sottili (AM grande)  meno fits.
2. Road Warrior per rimuovere i ghosts
4/5 – 128kp – RW – All
Annovi/Belforte
Gli upgrade riportano
la distribuzione dei
tempi del 4/5 su quella
del 4/4 !
4/5 – upgraded 4/5 – 4/4
Detector Ghosts
XFT
svx
SVT ha recentemente attivato il 4/5.
Complessita’ e tempo di esecuzione sono aumentati.
L1_TWO_TRK_PT2 L1_TWO_TRK2_&_TWO
_CJET5 Zbb
B physics
SVTconfiguration
4/5
# of fits
# of fits
32 kpatt 4/4
3.9
9.4
32 kpat 4/5 (now)
39.1
94
32 kpat 4/5 + RW
17.6
42
128 kpat 4/5 + RW
9.3
23
Detector ghost
4.3
14.5
ROAD WARRIOR e AM ++ riportano il
tempo di esecuzione a quello del 4/4 !
Accurate deadtime model (ModSim)
18
16
Total Dead Time
M. Schmidt
4/5+SVTupgrade  4/4
20
4/5+SVTupgrade+L2upgrade
4/5 now
14
12
Ini_lum=44*1030
10
3
8
6
4/4
RUN 168640
4/4L2UP-L2A 300Hz
4
4/4L2UP-L2A 300Hz
2
4/4NOUP-L2A 140 Hz
4/4NOUP-L2A 300 Hz
0
0
10
16
20
30
40
50
L1A rate (kHz)
Ini_lum=32*1030
Ini_lum= 17.5 *1030
Ini_lum=22*1030
17kHz
Trigger di muoni in avanti
(Annovi - Catastini – Cerri)
1<h<1.25 (FRONT) L1 ora:
BMU*BSU(F)*XFT11
BMU
1<h<1.25 BSU(F)
rate 8-16Hz @ 4E31
L2: RateLimited @ 0.7 Hz
1.25<h<1.5 BSU(R)
1.25<h<1.5 (REAR) L1 ora:
BMU*BSU(R)*TSU
Rate 200-400Hz @ 4E31
TSU
L2: RateLimited @ 1.3 Hz
Usiamo SVT*BMU*BSU per un unico trigger, senza bias in h !
Goal reiezione ~ 20-50.
•leptoni pronti di alto Pt  solo 30kpatterns 95% efficiente
per Pt>8 GeV e d0<500mm (ottima efficienza fino a 4 GeV).
Implementiamo il 4/5.
SVX
STUDIO del NUOVO TRIGGER
• Qualita’ delle tracce SVX only: studio su dati e MC
• Efficienza selezione L2: studio tagli su dati Z0 mm
• Regezione del fondo: studio su dati selezionati da L1 ora
Selection
# eventi
Z0
# eventi
L1_BMU_REAR
L1_MU
250
4678
match Df<2.5º
Pt>4 & 2<10
132
362
+ h match
126
213
Efficiency L2 sel.
0.50
Rejection L2 sel.
22
J/Psi: MC vs SVT
SVT: 2<10; |MCf0 – SVTf0|< 0.015
sPt/Pt2=0.08
MCCRV-SVTCRV
MCf-SVTf
MCPt-SVTPt
s(f)=0.007
QUALITA’ delle
tracce SVX only?
Limit: s(f) = 0.002,
sPt/Pt2 = 0.07
L1_MU data: offline vs SVT
SVT 2<10; |offlf0 – SVTf0|<0.015
s(f)=0.008
f(SVT)- f(offl)
sPt/Pt2=0.095
c(SVT)- c(offl)
f match
h match
Pt match
f effic.
h effic.
Pt effic,
60%
60%
60%
Scegliamo il trigger di livello 2: quali tagli?
fBMU–f0 offl
Z0 eff
~ 50%
Z0->mm data : Pt>4 & 2<10
fBMU–
0 offlfvs
0f
offl
BMU
(best)
fBMU–
0 SVTfvs
0 SVT
fBMU
(best)
5o
Pt>4 & 2<10+|fBMU–f0 SVT|< 5O
ff0BMU–
offl vs
f0foffl
BMU(best)
CUT
fBMU–f0 SVT
ff0BMU–
SVT fvs0 f
SVT
BMU(best)
f matching
cut
L1 MU data
Per stimare la reiezione
Reiezione fondo
~ 22
Conclusioni
• L’upgrade di SVT permettera’ un raddoppio
della banda passante di L1 ed e’ parte
fondamentale del DAQ upgrade.
• L’uso di tracce SVX only permette un
trigger inclusivo di muoni in avanti e di
abbassare le soglie di trigger per gli
elettroni nel plug.
Pisa:
Annovi
Bardi
Dell’Orso
Giannetti
Spinella
dottorando
ingegnere - art. 23
prof. Associato
dirigente di ricerca
assegnista INFN
Damiani
Sartori
Tripiccione
Cotta
Chiozzi
assegnista
assegnista
prof. Ordinario
tecnologo
tecnico
Ferrara:
(100%)
(100%)
(100%)
(100%)
(50%)
(10%)
(50%)
(10%)
(10%)
(20%)
“A Standard Cell based Content-Addressable Memory System for Pattern Recognition”
A. Cisternino et al., CERN/LHCC/98-36
TEMPI DI REALIZZAZIONE
• Nuova AM-board: inizio estate 2004 (Pisa)
durante estate 2004: test con FPGA (Pisa)
• Progetto prototipo AM-chip: luglio 2004 (Ferrara-Pisa)
consegna chip ~2 mesi – disponibile ad ottobre.
• Nuova LAMB: montare nuovo AM-chip a ottobre 2004 (Pisa)
• test del chip + scheda: ottobre – dicembre 2004 (Pisa-Ferrara)
• produzione: inizio 2005 (Pisa-Ferrara)
• installazione: estate 2005 (Pisa-Ferrara)
•
Altri DAQ/Trigger upgrade: previsti nel 2006
RUN Multiprojects di Europractice: nel 2003 tutti
i mesi eccetto luglio e Dicembre
http://www.europractice.imec.be/europractice/
Road Warrior: fattibilita’
in Pulsar  S. Belforte (~60 k$ Fermilab)
messa in opera entro fine 2003  F. Spinella
Backup slides
Il tempo morto (< 5%) genera limiti alla
banda passante dei 3 livelli
• ……………….
• L1 accept rate of 30kHz appears to be achievable
– Two SRCs, 7-bit digitization
– SVT improvements
– L2 upgrade
• L2 peak rate limited by Event-builder
J. Lewis
CDF CSL
Review
23 June 2003
– Current limit ~350 Hz
– EVB group: 450 is possible- TDC improvements coming
• Will keep up at high luminosity
• Level 3 Limitations
– Input: CPU power …..
– Output: Logging Rate……
Level 1 @Lum=40x1030 cm-2 sec-1
• Two Major Components
– Calorimeter Triggers: Jets, electrons, photons, etc.
In SVT: L1_JET10_&_SET90 (Higgs multijet)
~4-5 kHz
L1_TWO_TRK2_&_TWO_CJET5 (Zbb)
L1_MET15_&_TWO_TRK2 (Higgs Z  nn)
L1_TWO_TRK10_DPHI20 (Di TAU exotic)
L1_EM8
(Gamma + bjet)
L1_CEM4_PT4
(B electron)
L1_CMUP6_PT4
(B muon)
– Hadronic B Decays: Two XFT tracks
~2 kHz
~11-12 kHz
• Using three classes of B triggers
– Scenario A
• pT>2, pT,1+pT,2>5.5, opp. charge, Df<135; DPS for safety only
– Scenario C
• pT>2.5, pT,1+pT,2>6.5, opp. charge, Df<135; NO DPS
– Low PT
• pT>2, Df<90; Heavy DPS, saturate bandwidth
• Not considered for long-term
J. Lewis
CDF CSL Review
23 June 2003
50
45
40
35
30
25
20
15
10
5
0
SRC (Done)
SVT (? K$)
upgrade
Rate (Hz)
Rate (kHz)
Level 2 Predictions
Level 1 Predictions
XFT (2227 k$)
L2 (429 k$)
500
450
400
350
300
250
200
150
100
50
0
High-pt + Sc. C
High-pt + Sc. A
TDC (2132 k$)
EVB (680 k$)
L3 (631 k$)
upgrade
0
10 20 30 40 50 60 70 80 90 100
Luminosity (e30)
0
10 20 30 40 50 60 70 80 90 100
Luminosity (e30)
J. Lewis
CDF CSL Review
23 June 2003
20
Data Volume (Mb/s)
With baseline cuts,
saturate bandwidth at
~7e31 if 30 kHz allowed
@L1
18
High-pt + Sc. C
16
High-pt + Sc. A
14
12
CSL Bandwidth:
Aggressive
Trigger Model
To stay below 21Mb/s
Some physics
losses
10
CSL (?k$)
Offline (1M$)
upgrade
8
6
4
2
0
0
10 20 30 40 50 60 70 80 90 100
Luminosity (e30)
Year chip
boards
2003? 120 kE
10 kE (test b.)
5 kE
135 kE
2004
-
10 kE (protot.)
30 kE
40 kE
2005
53 kE
40 kE (produc.)
Ferrara
devel. Total
60 kE
153 k
Pisa
Road Warrior e’ pagato da USA: sottratti i
35 kE corrispondenti nel 2005 (grazie Stefano!)
Level 2 Operation
• Approximate Timing Diagram
1
Setup
5
Digitize
10
15
Time Since L1A (msec)
20
25
30
Silicon
SVX R/O
r-phi r-z
ISL R/O
R/O
L00 R/O
R/O (16us Read-All)
SVT
SVT Processing
Load in a
CF, m , track…Process and Load
Process in a
35
40
45
Unpack, Algorithms, TS Handshake
Ready to load next event
18
18
16
16
14
14
L1A
L1A rate
rate (kHz)
(kHz)
12
12
L1Arate
rate(2.4)
(2.4)
L1A
L1Arate
rate(2.87)
(2.87)
L1A
10
10
L1Arate
rate(3.9)
(3.9)
L1A
L1Arate
rate(4.15)
(4.15)
L1A
L1Arate
rate(4.15)B
(4.15)B
L1A
L1Arate
rate(5.0)
(5.0)
L1A
88
L1Arate
rate(3.5)
(3.5)
L1A
66
44
22
00
20
20
30
30
40
40
50
50
60
60
Ist. Lum. (10**30 sec-1 cm-2)
Inst.
70
70
80
80
3D info from SVT
Due categorie di tracce SVT:
1. (Dz=0) Tracce che entrano
escono dallo stesso barrel
2. Tracce che attraversano i
barrel. Conosciamo il sengo di h.
Una traccia SVT corrisponde ad una
traccia offline se Dz=0 oppure se Dz
ha lo stesso segno di h.
Z
DT1< Thr.
DT2< Thr.
L1 Trigger:
(DT1< Thr. OR DT2< Thr.) AND BSU
Camere dei MU (BMU) + scintillatori
esterni (BSU)
Come migliorare il fattore di
reiezione per il trigger di m
Migliorabile con semplici accorgimenti aggiuntivi:
1. Uso dell’informazione di hadron timing
2. Riduzione della finestra temporale per gli
scintillari BSU e TSU
3. Usare il beam constraint per il track fitter
• Migliora la risoluzione in Pt
• Riduce il numero delle tracce false
Z0 TRIGGER STUDY
0.9
0.9
0.8
0.7
5 GeV
Higgs bb (mass = 110 GeV)
Z0 ha efficienze minori (mass = 90 GeV)
RUN IB
Minimum
Bias events
Why 4/5 is more complex?
5/5
4/5
This road share
all hits with
the 5/5. It’s a
ghost.
4/5
4/5
These 3 roads
share all hits.
Two are
ghosts.
Ghosts are 60-70% of 4/5 roads.
Removing them speeds up 4/5 processing time.
NOW pattern recognition with 5 SVX layers uses
larger patterns w.r.t. 4 SVX layers
More fake roads and more hits inside roads
Solution: More AM  thinner patterns  reduce
fakes
4/5
Sorgenti di inefficienza
per m da Z0
Silicon &
clustering
wedge crossing
AM coverage
Ineff %
15
2 cut
10
5
5
Pt cut
h, f match
7
6
Tracking in 2 steps: find Roads,
then find Tracks inside Roads
Super
Pattern
Super Bin
Full
Resolution Hits
use most
significant
bits only
Road
Road
TRACKING WITH
PATTERN MATCHING
The Event
The Pattern Bank
The Associative Memory (AM)
• Dedicated device-maximum parallelism:
• each pattern has its private hardware to
compare with the event.
• Roads search during detector readout
AM =
BINGO PLAYERS
PATTERN 5
PATTERN 4
PATTERN 1
PATTERN 2
PATTERN 3
PATTERN N
HIT # 1447
Bingo scorecard
...
SVX only 2 distribution