Sezione di Bari LV PS system and DCS Domenico Elia – INFN Bari LV PS and regulators: current scheme, tests Regulator board: proto2, design considerations DCS: first PVSS based developments Domenico Elia ALICE SPD meeting - February 4, 2003 1 LV PS and voltage regulators (I) Sezione di Bari Tests at CERN (Michel, Petra … ): test performed with 10 chips (bus card A), Iload 5.5 A SEMTECH EZ1580 (7A) voltage regulators used 9 mt distance between chips and regulators detector works fine with such remote regulation (but with small variation of Iload, within 100 mA) grouping of ANALOG and DIGITAL powers also OK Domenico Elia ALICE SPD meeting - February 4, 2003 2 LV PS and voltage regulators (II) Sezione di Bari Current scheme: regulators outside magnet door (>10 mt from SPD): no need for rad-hard devices spaces, cabling, cooling issues much less critical reduced amount of power lines: 2 regulators each half-stave (instead of 7) 1 LV power source each half-sector VRs Internal PP Domenico Elia 10 mt ALICE SPD meeting - February 4, 2003 30 mt 3 LV PS and voltage regulators (III) Sezione di Bari Further activities in Bari: characterization of SEMTECH regulators test setup with long cables (11 mt between VR and load) ripple rejection and active load tests ELIND-30KL 38/80 and Wiener PL6012 as power sources other commercial regulators with remote sensing Antonio’s talk Domenico Elia ALICE SPD meeting - February 4, 2003 4 Voltage Regulator board (I) Sezione di Bari New prototype: still using ST-L4913 rad-hard voltage regulators power channels needed for 2 half-staves (total of 8 VRs: 4 x single + 2 x parallel schemes) ALTERA FPGA implementing control logic (VERILOG code written by Michele Caselle) INHIBIT and OVC flags available for control functionality full board control via JTAG (still under test) Domenico Elia ALICE SPD meeting - February 4, 2003 5 Voltage Regulator board (II) Sezione di Bari LV input HV input to load JTAG connector TAP ALTERA FPGA control via JTAG Domenico Elia ST-L4913 VR ALICE SPD meeting - February 4, 2003 6 Voltage Regulator board (III) Sezione di Bari LV input HV input to load TCK, TMS, TDI, TDO and TRST* INHIBIT OVC With a new Inhibit configuration ALTERA FPGA for JTAG Control Domenico Elia ALICE SPD meeting - February 4, 2003 7 Voltage Regulator board (IV) Sezione di Bari Concerns for final VR board design: number of LV channels to provide segmentation, total number of boards location of the board and related issues choice of voltage regulator on-board control issues (FPGA etc…) connection with external world (JTAG, other bus …) Domenico Elia ALICE SPD meeting - February 4, 2003 8 DCS developments (I) Sezione di Bari Test station setup in Bari lab: (in collaboration with Leonid Vinogradov) PC with Win2K devoted to SPD control developments PVSS2 and Framework 1.2 software installed HV control sector: CAEN HV OPCserver 2.0 installed and configured on same PC CAEN SY1527 equipped with A1519 board (12 HV channels) Domenico Elia ALICE SPD meeting - February 4, 2003 9 DCS developments (II) Sezione di Bari Framework selection of SY1527 with 1 HV board PVSS2 Framework CAEN OPC Server CAEN SY1527 HV board: A1519 Domenico Elia ALICE SPD meeting - February 4, 2003 10 DCS developments (III) Sezione di Bari SPD HV-LV preliminary control panel Hierarchical structure Domenico Elia ALICE SPD meeting - February 4, 2003 11 DCS developments (IV) Sezione di Bari Example of monitoring panels for 12 HV channels (1 half-sector) Domenico Elia ALICE SPD meeting - February 4, 2003 12 DCS developments (IV) Sezione di Bari LV control sector: WIENER PL6021 PS equipped with Kvaser PCIcan-Q card Kvaser card drivers installed and tested test of CANbus in progress Wiener OPC server not available contacts with ALICE DCS and IT/CO people: SLiC.OPCserver next: continue integration of control subsystems Domenico Elia ALICE SPD meeting - February 4, 2003 13