Curriculum Vitae
Paolo Grani
Personal profile
Place of residence Via Cupa n. 15, 01014 Montalto di Castro (VT), Italy.
Cell-Phone-Number
Personal-Email
Citizenship
Date of birth
Key skills
+39-349-4721830
[email protected]
Italian
09/22/1984
Factories operating in the fields of computer hardware manufacturing and software
companies that use computer equipment and computer networks as part of their
production processes, service company or consultancy.
Technological industries, R&D.
Education
Ph.D.
Doctoral Degree in Engineering and Science of Information (2012 – 2015), XXVII
Cycle, University of Siena, via Roma 56, 53100 Siena (SI), Italy.
Final dissertation title: “From Electro-Optical to All-Optical Network on Chip Solutions for
Serving Future Chip Multi-Processor Systems”.
Master
Master's Degree in Computer Science Engineering (2007 – 2009),
curriculum Networking & Multimedia, University of Pisa, Computer Engineering,
via Diotisalvi, 56100 Pisa (PI), Italy.
MAC Protocols, Internetworking, Mobile IP, Routing, Transport protocols, ATM
Advanced Network Architectures and Wireless Systems as IntServ, DiffServ,
Packet Scheduling Algorithms, MPLS, VPN, IEEE 802.11, IEEE 802.16, QoS,
Network security issue like symmetric and asymmetric encryption, Digital
signatures, Public Key infrastructures, OpenSSL, Security in 802.11, IPSec, SSL .
Bachelor
Bachelor's Degree in Computer Science Engineering (2003 – 2006), University of
Pisa, Computer Engineering, via Diotisalvi, 56100 Pisa (PI) , Italy.
Preparation on scientific-methodological basis (mathematics, physics and
foundations of computer science) to interpret and describe engineering problems,
lessons learned in engineering content across sectors (electrical, electronics,
telecommunications, automation) and teachings of the industry Engineering (logical
networks, electronic computers, operating systems, computer networks).
High School License
Diploma at Liceo Scientifico Galileo Galilei (2002 – 2003), Strada
Provinciale Porto Clementino, 01016 Tarquinia (VT), Italy.
General knowledge.
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Language
Italian native
Understanding
Other Languages
Listening
Reading
Spoken
Oral interaction
Written
Oral production
English
C1
Fluent User
C1
Fluent User
C1 Fluent User C1 Fluent User
French
B2
Indipendent
B2
User
Indipendent
User
B2
C1
Fluent User
Indipendent
Indipendent
B2
B2
User
User
Indipendent
User
Personal skills
Social skills
Excellent interaction with the public and high propensity for teamwork.
Organizational skills and willingness to problem solving.
Excellent skills in spoken or written report.
Computer skills
Excellent knowledge of key network infrastructure, computer architecture and key
issues of information security (digital certificates, digital signature ...).
Programming Languages
Very good knowledge of Java (J2SE and J2ME), C/C++/Symbian C + +, PHP, CSS
and HTML, JavaScript, TCL, NesC, linux shell scripting.
Operating systems
Good knowledge of Windows OS (9x, NT, 2000, XP).
Very good knowledge of UNIX-like operating systems (specifically Debian based
systems).
Software and Applicative Tool
Experience using the following IDEs:
Eclipse/Netbeans;
Carbide.
Experience using OpenCA and OpenSSL for managing PKIs:
Managing templates for certificates;
Creation / modification of CA;
Operations Issuing / revoking user certificates.
Experience in Web Services Security:
WS-Security, SAML Tokens, WS-Trust and WS-SecureConversation.
Knowledge and experience using the following standards:
XML 1.0, SOAP 1.1, WSDL 1.1, SAML 1.1, X.509 Certificates, SQL, W3C XML
Signature 1.0, W3C XML Encryption 1.0, XACML 2.0, 3.0 .
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Tools:
Subversion, GNUPlot, Doxygen, Slurm, SSH.
Simulators:
GEM5, NS2.
Modeling languages:
UML, Verilog, VHDL, WSDL.
Middleware:
JavaRMI, CORBA.
Others:
Apache, phpMyAdmin,
OpenOffice, LaTeX.
MatLab/Simulink,
SciLab/SciCos,
Microsoft
Office,
Configuring and maintaining CISCO routers and LAN switches.
Work experiences
January 2012 – January 2015 (3 years).
PhD student at Department of Information Engineering, Mathematical
and Computer Sciences, University of Siena, Italy.
My research interests include multi- and many-core architectures, on-chip networks
(NoC), cache coherence protocols and architectural support for parallel programming.
Scalable cache coherence protocols (i.e. state-of-the-art MOESI) and on-chip
interconnection networks require new innovations to support many-core architectures.
Current and future Chip Multi-Processors systems (CMPs) running modern
multithreaded applications (i.e. PARSEC 2.1 benchmark suite) require high-bandwidth
and low-latency interconnection for efficiently managing coherence protocol evolution.
However, also due to the emerging wire delay issues traditional electrical NoC (eNoC)
designs have troubles in fulfilling these requirements while maintaining an acceptable
power consumption. On-chip nanophotonic technologies are now considered a viable
solution for fulfilling future system bandwidth demands, low-latency communication
and reduced power consumption communication but great care is needed in the
design and management of photonic structures to actually take advantage of these
features within complex CMPs. My research to date has focused on analyzing these
facets and specifically my interest is in studying performance and energy consumption
behavior of optical on-chip network (ONoC) using a full system (booting Linux 2.6
operatiing system), cycle accurate simulator (GEM5).
March 2011 – July 2014 (3 years and 3 months).
Collaborator on Photonica Project, University of Siena, Italy
My primary research interests lie in on-chip interconnection networks and cache
coherence protocols for many-core architectures. My current research re-examines and
challenges some of the design assumptions that hold true for shared-memory
multiprocessors when explored in the context of chip multiprocessors. As we migrate
many of these design choices on-chip, it is worthwhile to examine their suitability and
present novel solutions (photonic interconnection links) that are attractive in term of
performance and energy consumption in the unique environment of a many-core
architecture. The goal of this research is to carefully consider communication
requirements (as dictated by the coherence protocol and software), design the
interconnection to better serve the coherence protocol and improve the cache
coherence protocols and high-level communication mechanisms to better leverage the
functionality of the on-chip interconnection network
(https://sites.google.com/site/photonicaproject/home).
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February 2010 - February 2011 (12 months).
Software engineer at the Institute of Informatics and Telematics (IIT)
National Research Council (CNR) in Pisa, Italy.
Study and implementation of a system for profiling the user based on assertions
exported as XML web service in the scope of the Regione Toscana Tuscany VISITO
project (http://www.visitotuscany.it/).
Study and implementation mechanisms of parental controls for mobile devices based
on Symbian operating system with particular regard to the recognition and
classification of images and videos containing pornographic material
(http://icaremobile.iit.cnr.it/index.php/it/).
October 2009 - February 2010 (6 months).
NOC Specialist Welcome Italy, Massarosa (LU), Italy.
Position held: Network & Services Management. Control of physical and logical
function of a national network infrastructure through an ongoing monitoring to prevent
disruptions, anticipate customer requests for technical assistance and reduce recovery
time of services in case of failure.
Scientific Publications
Boosting Multi-Socket Cache-Coherency with Low-Latency Silicon Photonic
Interconnects, ICNC’15 (Paolo Grani, Robert Hendry, Sandro Bartolini and Keren
Bergman), to appear.
Integrated Cross-Layer Solutions for Enabling Silicon Photonics into Future Chip
Multiprocessors, IMS3TW’14 (Paolo Grani, Sandro Bartolini, Emanuele Furdiani, Luca
Ramini and Davide Bertozzi).
Towards Compelling Cases for the Viability of Silicon-Nanophotonic Technology in
Future Manycore Systems, NOCS’14 (Paolo Grani, Luca Ramini, Herve Tatenguem
Fankem, Alberto Ghiribaldi, Marta Ortin-Obon, Anja Boos and Sandro Bartolini).
Simultaneous Optical Path-Setup for Reconfigurable Photonic Networks in Tiled CMPs,
HPCC’14 (Paolo Grani, Sandro Bartolini).
From Hybrid Electro-Photonic to All-Optical On-chip Interconnections for Future CMPs,
HPCS’14 (Paolo Grani).
Design Options for Optical Ring Interconnect in Future Client Devices, ACM Journal on
Emerging Technologies in Computing Systems (JETC), 2014 (Paolo Grani, Sandro
Bartolini).
Assessing the Energy Break-Even Point between an Optical NoC Architecture and an
Aggressive Electronic Baseline, DATE'14, 2014 (Paolo Grani, Luca Ramini, Herve
Tatenguem Fankem, Alberto Ghiribaldi, Sandro Bartolini and Davide Bertozzi.
Co-tuning of a Hybrid Electronic-Optical Network for Reducing Energy Consumption in
Embedded CMPs. Accepted at MES '13, ACM Internation Workshop on Manycore
Embedded System, to be held in conjunction with the 40th International Symposium
on Computer Architecture (ISCA 2013), Tel-Aviv, Israel, June 23-27, 2013. (Paolo
Grani, Sandro Bartolini).
Contrasting Wavelength-Routed Optical NoC Topologies for Power-Efficient 3D-stacked
Multicore Processors using Physical-Layer Analysis, DATE'13, 2013 (Paolo Grani, Luca
Ramini, Sandro Bartolini, Davide Bertozzi).
A Simple On-chip Optical Interconnection for Improving Performance of Coherency
Traffic in CMPs, DSD, EuroMicro conference, 2012 (Paolo Grani, Sandro Bartolini).
Simple On-chip Optical Interconnection for Improving Performance in Clustered CMPs,
Poster In ACACES'12, Eighth International Summer School on Advanced Computer Architecture and Compilation for High-Performance and Embedded Systems Fiuggi, Italy,
Sunday July 8 - Saturday July 14, 2012 (Paolo Grani, Sandro Bartolini).
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Professional activities
Technical Program Committee Member of: The second International Workshop on
Exploiting Silicon Photonics for energy-efficient heterogeneous parallel architectures
(SiPhotonics'2015).
Paper reviewer of: Microprocessors and Microsystems Journal (MICPRO).
Paper reviewer of: IEEE International Conference on High Performance Computing and
Communications (HPCC 2013).
Technical Program Committee Member of: The first International Workshop on
Exploiting Silicon Photonics for energy-efficient heterogeneous parallel architectures
(SiPhotonics'2014).
Paper reviewer of: IEEE International Conference on High Performance Computing and
Communications (HPCC 2014).
Memberships
European Network of Excellence on High Performance and Embedded Architecture and
Compilation (HIPEAC).
Association on Computer Machinery (ACM).
ACM Special Interest Group on Computer Architecture (SIGARCH).
IEEE Membership (student).
Awards
Didactical Experiences
Winner of a travel grant from SIGARCH to participate to the ACM/IEEE International
Symposium on Computer Architecture (ISCA 2013) conference in Tel-Aviv.
Implementation of simple remote commands service (both client and server sides)
using socket in a Unix environment.
Implementation of a fire and thief alarm with mobile sensors.
Implementation of a simple compressor/decompressor based on Huffman code (Unix
environment).
Modification of some functionalities of Judy library for associative array in FreeBSD
environment.
Specialties
Java Security Architecture, Policy Implementation and Syntax, X.509 Certificate and
Certificate Revocations Lists (CRLs), Java Cryptography Architecture, TPM tools,
Advanced Network Architecture, sensors network, Computer Memory Architecture,
Memory optimization, coherence protocol, nanophotonic network on chip (NoC),
simulation environments.
Interests
Networking & Multimedia.
Computer Architecture.
Information Security.
Memory transactions and Coherence protocols.
Networks on Chip (NoCs) and Chip Multi Processors systems (CMPs).
DISCLAIMER PROCESSING PERSONAL DATA
I authorize to handle my personal data according to D. Decree Law 196/2003 for the purposes of recruitment and assessment staff.
Siena, 01/22/2015
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