Novita’ FTK da luglio
P. Giannetti per il gruppo FTK
• Review Amchip - lieve cambiamento alla schedule
• Il problema del cooling ed I tests a punto 1
• Test miniasic e ordini di AMchip05
• Le schede
• FTK nel TDR del TDAQ
• Richieste e responsabilita’
Legenda
Asic submission
Stand-alone test
Integrated test
Global Integration test
Production - Installation
Review
Months
Tasks
Dual Output HOLA
FTK Input Mezzanine
Data Formatter
Miniasic
AMchip05
AMchip06
AMBSLP-Mini-LAMBSLP
AMBSLP-LAMBSLP
AUX CARD
Second Stage Board (SSB)
FTK Level-2 Interface Crate (FLIC)
cooling
TDR schedule
Review AMchip
Review
Boards
7
8
9 10 11 12
2013
1
2
3
4
Review cooling
@point 1
5
w DF/IBL/RODs
test
w AUX
test
ta peout
6 7 8 9 10 11 12
2014
Global Int.
Global Int.
Global Int.
test
test
test
1
2
3 4
2015
5
test
tapeout
test
MOU schedule
test
aux
w DF
w FLIC/AUX
w SSB - ROS
w AM05AUX
w AMBSLP
Global Int.
Global Int.
Global Int.
Global Int.
wAM06
8-16 PUs
8-16 PUs
6
2 Gb/s data transfer
• MiniAsic - ongoing tests at Milan –
Silicon Creation Serializer/Deserializer OK
• Design of AMchip05
(LPNHE-MI-LNF-PI-) advanced –
Submission during october
• Design of AMchip06 expected for spring
2014 – as early as possible to maintain
the commissioning milestone
BGA package common to AMchip05 & 06
defined – Amchip05 order started
PACKAGE
ASE
DESIGN
VSSS
VSSS
VSSS
VSSS
VSSS
VSSS
PATTIN1H
OLD
PATTIN0H
OLD
VSSS
VSSS
VSSS
VSSS
VSSS
VSSS
VSSS
VSSS
VSSS
VSSS
VSSS
VSSS
VSSS
VSSS
VSSS
VSSS
VSSS
VSSS
VSSS
VSSS
VSSS
VSSS
VSSS
VSSS
VSSS
VSSS
VSSS
VSSS
VSSS
VSSS
PATTIN1_
P
PATTIN1_
N
VSSS
VSSS
VSSS
VSSS
VDDIO
VDDIO
VDDIO
VDDH
VSSS
VSSS
VDDIO
VDDIO
VDDIO
VDDA
VSS
VDDIO
VSS
VSS
VDDIO
VSS
VDDIO
VDDIO
VSS
VDDIO
VDDIO
VSS
VSS
VSS
VSS
VSS
VSS
VDDIO
VDDIO
VDDIO
VSS
VSS
VDDIO
VDDIO
VDDFC
VDDFC
VSS
VSS
VDDIO
VDDIO
VDDIO
VSS
VSS
VDDIO
VDDIO
VDDIO
VSS
VSS
VDDIO
VDDIO
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
TMS
TDI
INIT
TRST
VSSS
H1_P
VSSS
H3_P
VSSS
H5_P
VSSS
H7_P
VSSS
VSSS
PATTOUT
HOLD
VSSS
VSSS
VSSS
VSSS
VSSS
H1_N
VSSS
H3_N
VSSS
H5_N
VSSS
H7_N
VSSS
VSSS
VSSS
VSSS
VSSS
VSSS
VSSS
VSSS
VSSS
VSSS
VSSS
VSSS
VSSS
VSSS
VSSS
VSSS
VSSS
VSSS
VSSS
VSSS
VSSS
VSSS
VSSS
VSSS
VSSS
VSSS
VSSS
VDDIO
VDDIO
VSSS
VSSS
VDDIO
VDDIO
VSSS
VSSS
VDDIO
VDDIO
VDDIO
VSS
VDDIO
VDDIO
VSS
VSS
VDDIO
VDDIO
VSS
VSS
VSSS
H0_P
VSSS
H2_P
VSSS
H4_P
VSSS
H6_P
VSSS
VSSS
H0_N
VSSS
H2_N
VSSS
H4_N
VSSS
H6_N
VSSS
VSSS
VSSS
VSSS
VSSS
VSSS
VSSS
VSSS
VSSS
VSSS
VSSS
VSSS
VSSS
VSSS
VSSS
VSSS
VSSS
VSSS
VSSS
VDDH
VDDH
VSSS
VSSS
VSSS
VSSS
VSSS
VSSS
VSSS
VDDH
VDDA
VDDA
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDH
VDDA
VSS
VDDA
VDDA
VDDA
VDDA
VDDA
VDDA
VDDA
VSS
VSS
VSSS
VSSS
VSSS
VSSS
VSSS
VSSS
VSSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDDFC
VDDFC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDSERD VDDSERD VDDSERD
VSS
ES
ES
ES
VDDSERD VDDSERD
VDDIO
VSS
ES
ES
VDDSERD VDDSERD
VDDIO
VDDIO
ES
ES
VDDSERD VDDSERD
VDDIO
VDDIO
ES
ES
VDDIO
VDDIO
VDDFC
VDDFC
VDDIO
VDDFC
VDDFC
VDDFC
VDDFC
VDDFC
VDDFC
VDDFC
VSS
PATTIN0_
P
PATTIN0_
N
PATTOUT
_P
PATTOUT
_N
VSSS
VSSS
VSSS
VSSS
VSSS
VSSS
VDDSERD
VDDH
VDDH
ES
VDDSERD
VDDA
VDDA
ES
VDDSERD VDDSERD
VSS
ES
ES
VDDSERD VDDSERD
VSS
ES
ES
VDDSERD VDDSERD
VDDIO
ES
ES
VDDSERD
VDDFC
VDDIO
ES
VDDIO
VDDIO
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VDDFC
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSSA_LVD
VDDCORE VDDCORE VDDCORE VDDCORE VDDCORE
VDDCORE VDDCORE VDDCORE VDDCORE VDDCORE
S
VDDFC
VDDFC
VDDFC
VDDIO
VDDFC
VDDFC
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VSS
VSS
VSS
VSS
VSS
VSS
VDDFC
VDDFC
VDDIO
VDDIO
VSS
VSS
VDDIO
VDDCORE VDDCORE
VDDCORE VDDCORE VDDCORE
VDDFC
VDDFC
VDDIO
VDDIO
VSS
VSS
VDDIO
VDDCORE VDDCORE VDDCORE
VDDIO
VDDCORE VDDCORE VDDCORE
VDDFC
VDDFC
VDDIO
VDDIO
VSS
VSS
VDDIO
VDDIO
VDDCORE VDDCORE VDDCORE VDDCORE VDDCORE VDDCORE
VDDIO
VSS
VSS
VDDIO
VDDIO
VDDCORE VDDCORE VDDCORE VDDCORE VDDCORE VDDCORE
VDDIO
VSS
VSS
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
VSS
VSS
VDDIO
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
VSS
TCK
VSS
VSS
VSS
VSS
VSS
VSS
DTEST
TDO
VSS
VSS
VSSA_LVD
S
VSSA_LVD
VDDCORE VDDCORE VDDCORE VDDCORE VDDIO
VDDIO
VDDIO
S
VSSA_LVD VSSA_LVD
VDDCORE VDDIO
VDDIO
VDDIO
VDDIO
VDDIO
S
S
VSSA_LVD VSSA_LVD VSSA_LVD
VSS
VSS
VSS
VSS
VSS
S
S
S
VDDA_BG VSSA_BG VDDA_LV VSSA_LVD
VSS
VSS
CLK_N
CLK_P
REF
REF
DS
S
VDDCORE VDDCORE VDDCORE VDDCORE VDDCORE
VDDIO
VDDIO
AMCHIP
status
Responsabile A. Lanza (PAVIA)
CAEN
OPTION
Rack Y.05-09.A2
SETUP for COOLING TESTs
at Point 1
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
TURBINE
HEAT EXCHANGER
9U VME bin
(AM PU)
Fan tray
HEAT EXCHANGER
External PS unit
Fan tray
HEAT EXCHANGER
9U VME bin
(AM PU)
Fan tray
Closing panel
Air deflector
Network switch
Rack Y.05-09.A2
52
51
50
49
48
47
46
45
44
43
42
41
40
39
38
37
36
35
34
33
32
31
30
29
28
27
26
25
24
23
22
21
20
19
18
17
16
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
TURBINE
HEAT EXCHANGER
External PS unit
HEAT EXCHANGER
9U VME bin
(AM PU)
Fan tray
Closing panel
HEAT EXCHANGER
External PS unit
HEAT EXCHANGER
9U VME bin
(AM PU)
Fan tray
Closing panel
Air deflector
Network switch
BOARDS
• FTK_IM prototype compatible with DF via FMC connector.
• Problem with power generator solved (changed component)
• Output to DF tested up to 400 MHz (design) for some lines.
• New requirement from DF: more lines at 400MHz required → new version needed
FRASCATI / WASEDA
La nuova scheda AMBSLP
just arrived – under test
XILINX ARTIX 7 in place of
SPARTAN 6
Smaller LAMBS → normal shape
High Density connectors
NO PARALLEL BUSES
ONLY SERIAL LINK
CONNECTIONS
miniLAMBSLP and
LAMBSLP
miniLAMBSLP
BGA 23x23
LAMBSLP
READY to order
QFN64
HW is OK but…. TDAQ - TDR…..
• I samples dalla produzione ufficiale di ATLAS per
rifare I plots di FTK con IBL incluso nella
simulazione non sono ancora disponibili.
• Integrazione con il sistema di produzione ha
richiesto lavoro addizionale ed imprevisto, sample
di calibrazione del sistema arrivati con 1 mese di
ritardo
• Esiste il capitolo 8 pronto su FTK, ma I plot sono
vuoti → non possiamo essere sicuri di riuscire
ad ordinare AMchip06 nel 2013 se
approvazione FTK ritarda - proponiamo di
spostare i fondi (200 keuro) al 2014
Richieste
SBLOCCO SJ 2013:
solo 5 k€ su Pisa (non core) per completare miniLAMB e LAMBSLP
PER IL 2014:
FRASCATI: Produzione mezzanine
FTK_IM -> 135 keuro; CPU ATCA (non core) 7 keuro.
PISA: schede e chips per 20 AMBSLPs -> 30
Pisa + 10 keuro SJ di contingenza.
MILANO:
1. AMchip06 MLM masks 200 keuro (I 195 keuro recuperati dal 2013 + 5)
2. tests AMchips alla Microtest 50 keuro + 50 SJ alla definizione finale del costo.
PAVIA:
consumo per test di raffreddamento e sviluppo del controllo del power supply: 5 keuro
TOT = [135 + 30 + 250] core + [7+5] (not core) =
415 k€ (core) + 12 k€ (non core) + 60 k€ SJ
RESPONSABILITA’ ITALIANE IN FTK
FTK team organization
Deputy Project Manager - P. Giannetti (Pisa)
Task LeadersHardware
FTK_IM - M. Beretta (Frascati)
AMBoard - M. Piendibene (Pisa)
LAMB – P. Giannetti (Pisa)
AMBoard and LAMB firmware - D. Magalotti (Perugia)
AM chip - A. Stabile (Milan),
System Integration
Tests & board integration in the Vertical Slice - M. Piendibene (PI)
DAQ integration: Vertical Slice/Demonstrator - A. Annovi (Frascati)
Rack integration including power supplies, cooling, & safety - A. Lanza (Pavia)
Interface to level-2 - A. Negri (Pavia), A. Annovi (Frascati)
FTK simulation - G. Volpi (LNF)
THIS IS THE PAST: project leader will be voted and
will nominate all the others
Conclusions
• Hardware development is ok
• The collaboration is strong with new important
entries
• Simulation and performance studies with IBL
accumulated a significant delay
MILESTONES
"Test AMchip05 completo" milestone di fine giugno
"Completa integrazione AMBSLP in FTK con AMchip05"
milestone di dicembre.
AMchip05 design
•
•
•
LVDS @ 2GHz: 11 SERDES (2 pattern in, 1 pattern out, 8 hit buses)
LVDS @ 100 MHz: CLK
single-ended control signals: JTAG Init, Dtest, Holds
14
Changes in LOGIC (LPNHE-Milan):
o SERDES I/O @ 16 bits (2 DC)
o
o
o
o
(AMchip04 was 15 bits 3 DC. Internally it's always 18 bits with
configurable DC)
Two pattern inputs one pattern output
(merge of pattern streams)
1-layer match threshold (other thresholds: never, 8, 7, 6,
always)
double width mode (4 bus - 32 bit)
optional continuous readout mode
(AMchip04 was event based only)
New features
wrt AMchip04
Change for implementation of design
o Majority inside pattern becomes full custom (MILAN)
o New Low Power full custom cell for pattern (LNF)
Milan
15
Not USA responsabilities
cost sharing – 2014 -2017 – TDR status
FTK Am & FTK_IM
AMBSLP-LAMBSLP
80 '14; 80 '15; 390 '16-'17
DF mezzanine - ITA
2014
DF mezzanine - Waseda
2014
Am05 12 mm^2 MPW
2013
100 PBGA1 for AM05
2013
AMchip06 MLM masks
2013
eng lot 9 wafers for first AMchip06 production
package PBGA for AMchip06 +40
AMchip06 production test
~50wafers: 2 lots of AMchip06 2015 - 2016-17
PBGA production 9000 pieces for AMchip06
SUPER TOT
TOT k€
550
135
135
45,00
18,00
410,00
55,00
20,00
120,00
300,00
35,00
1823,00
UNI-GE
ITA
30
500
135
Waseda
Heidelberg
USA AM Melburne
AUTH
Parigi
10
10
STOT
135
45
0
20
200
190
xx
55
60
120
200
90
1175
100
35
170
100
290
ITALIA core 2013:
= 220 keuro AMchip06
ITALIA core 2014: 135 (FTK_IM)+ 30 (AMBSLP) + 120 (tests parzialmente SJ)
= 285 keuro
ITALIA core 2015: 80 (AMBSLP)+200 wafers = 280 keuro
ITALIS core 2016-2017:
= 390 keuro AMBSLP
+ qualche spesa piccola non-core
10
10
1845
16