Sensor wafer layout:
a first look
Massimiliano Fiorini
(Università degli Studi di Ferrara – INFN Ferrara)
Gigatracker Working Group Meeting
15th July 2008, CERN
Sensor wafer
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Sensors from FBK-irst
4” Si wafer (10.16 cm diameter)
Constraint: metal ring to clamp the wafer
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useful wafer surface reduced to 84.9 mm diameter
Exercise: put 2 full sensors on the same wafer,
together with “1/10” sensors (match r-o chip
size) and demonstrator-size sensors
Assumptions:
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0.5 mm for guard rings (is it enough?)
0.5 mm for dicing lane (could this be reduced?)
Wafer layout (sketch)
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Full sensor: 60 × 27 mm2  61 × 28 mm2
1/10 sensor size: 12 × 13.5 mm2  13 × 14.5 mm2
Sensor for demonstrator: 2 × 5 mm2 or 3 × 5 mm2
4” wafer
Wafer layout (with dimension)