CARLOSv3 0.25mm Rad-Hard
&
ALICE SDD DAQ Chain Test
Samuele Antinori - Davide Falchieri
Alessandro Gabrielli
Enzo Gandolfi – Massimo Masetti
INFN Bologna 2003 - Davide Falchieri
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9+4
A
P
½ SDD
½ SDD
P
A
9+4
JTAG
CARLOS
v3
5
16
tx_en
cav, dav
TLK-1501
GOL
DES
200 m
16
rxdata
L0
rx-ck
busy
CTP
QPLL
ck (40 MHz)
serial back-link
4
JTAG
A
P
½ SDD
½ SDD
P
A
9+4
JTAG
9+4
5
16
tx_en
cav, dav
CARLOS
v3
TLK-1501
GOL
DES
200 m
CARLOS
rx
16
rxdata
32
5
rx-ck
JTAG
DDL
7
QPLL
ck (40 MHz)
serial back-link
JTAG 4
pRORC
TTCrx
INFN Bologna 2003 - Davide Falchieri
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State of the Art (June 2002 – June 2003)
The main topics we have been facing are the following:
 Design, realization and test of 2 digital ASICs: CARLOSv3 and LVDS-CMOS
converter rad-hard in 0.25mm CMOS technology by CERN EP-MIC (Marchioro)
 Test of CARLOSv3 and LVDS-CMOS on a dedicated test board with Tektronix
instruments
 Test of CARLOSv3 with optical link (TX + RX from Lab. Elettronica INFN BO)
 Design of a DAQ chain from CARLOSv3 to the CERN DDL:
interface board CARLOSv3_rx (VIRTEXII FPGA)
 Test of the DAQ chain both in Bologna and at CERN
Even thanks to the portable DAQ chain we have been able to run the data acquisition
through DDL at CERN: FOR THE SECOND YEAR THIS WAS THE FIRST ALICE
DDL CHAIN TESTED AT CERN
INFN Bologna 2003 - Davide Falchieri
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CARLOSv3 pictures
2D Compressor for
Core
40 MHz SRAMs (2-Read 1-Write)
100
Pads
Final
Layout
4x4 mm2
Full-Custom
RAMs for the
2D-Compressor
40MHz Clock
CARLOSv3 chip yield 33 out of 35 packaged chips
INFN Bologna 2003 - Davide Falchieri
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2D Compressor HW Implementation
Programmable
up to 256
Time-Samples
Up to 256 x 9-bit dual port Rad-Hard SRAM
Up to 256 x 9-bit dual port Rad-Hard SRAM
HALF-DETECTOR
matrix from AMBRA
Potential Clusters
5 data at a time are evaluated by taking
into account the 2 thresholds of the 2D
algorithm
If the requirements are met the central
cluster position and its amplitude are packed
and transmitted
 After each event data set received from
AMBRA, CARLOS disables AMBRA for 256
clock period for emptying the successive
FIFOs
Off border data are forced to zero!
INFN Bologna 2003 - Davide Falchieri
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CARLOSv3 with LVDS-CMOS Test Board (Sketch)
INPUT STRIP
CONNECTOR
Right
Hybrid
Left
Hybrid
LVDS
CMOS
TEST STRIP
CONNECTOR
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CARLOSv3
OUTPUT STRIP
CONNECTOR
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DDL
CARLOSv3_rx
The board
interfaces 2
AMBRAs
Torino
Bologna
INFN Bologna 2003 - Davide Falchieri
CERN/EP-AID
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CARLOSv3 with LVDS-CMOS Test Board (Photo)
INPUT STRIP
CONNECTOR
LVDS
CMOS
TEST STRIP
CONNECTOR
CARLOSv3
OUTPUT STRIP
CONNECTOR
CARLOSv3 fully tested on:
 JTAG,
 Serial Back-Link
 Data-Compression
Pattern
Generator
State
Analyzer
Test Patterns made of:
ten 50k-word events
Sockets
50 packaged chips
CQFP100
Lvds-Cmos chip yield 15/15 ---- CARLOSv3 chip yield 33/35
INFN Bologna 2003 - Davide Falchieri
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Test of CARLOSv3  Optical-Link  CARLOSv2_rx
(Sketch)
Pattern
Generator
CARLOSv3
CARD
SERIALIZER
CARD
DESERIALIZER
CARD
OPTICAL
LINK
2002 CARLOSv2_rx
State
Analyzer
GOL
TLK
1501
CARLOSv2_rx
SIMU
JTAG signals
and Back-Link
Bologna
Bologna INFN LAB
CERN/EP-MIC
INFN Bologna 2003 - Davide Falchieri
CERN/EP-AID
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Test of CARLOSv3  Optical-Link  CARLOSv2_rx
(Photo)
Pattern
Generator
SERIALIZER
CARD
OPTICAL
LINK
DESERIALIZER
CARD
2002 CARLOSv2_rx
SIMU
CARLOSv3
CARD
State
Analyzer
GOL
INFN Bologna 2003 - Davide Falchieri
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CARLOSv3_rx Test Board (Sketch)
STRIP
CONNECTOR
CARLOS v3
CARLOS v3
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CARLOSv3_rx
PROM
CONNECTOR
for DDL
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Final solution, still to be
fully redesigned, will
receive data from about
22 CARLOS chips
SIU
SIMU
Bologna
INFN Bologna 2003 - Davide Falchieri
DIU
pRORC
CERN/EP-AID
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AMBRA  CARLOSv3 CARLOSv3_rx DDL
for TEST-BEAM (Sketch)
CARLOSv3
BOARDS
CARLOSv3_rx
Pattern
Generator
At CERN Serial Back-Link and
JTAG signals must be provided
through DDL
AMBRA
AMBRA
DIU
pRORC
SIU
AMBRA
AMBRA
4-bit JTAG
Serial Back-Link
SIMU
State
Analyzer
Serial Back-Link
4-bit JTAG
Torino
Bologna
Bologna
INFN Bologna 2003 - Davide Falchieri
CERN/EP-AID
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Test of the chain with the DDL at CERN (06/06/03)
CARLOSv3
test-bench
(50-kword event)
SIU (DDL)
Up to 3M events
transferred
Optical Fiber
to Linux PC
(DDL)
CARLOSv3_rx
For the second year this was the first ALICE DDL chain
tested at CERN: to be presented next week at DAQ meeting
INFN Bologna 2003 - Davide Falchieri
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Test of the LAST YEAR chain with the DDL at CERN (14/06/02)
CERN INTERNAL REPORT ALICE-INT-2002-24
This year we are
planning to write
another internal note
for the new DAQ test
INFN Bologna 2003 - Davide Falchieri
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Bologna work plan 2003

CARLOSv4: further test chip before production:
estimated area always 4x4 mm2

Further tests at CERN for tuning the DAQ chain:
CARLOSv3-CARLOSv3_rx-DDL

Test-Beam on August 2003 with front-end electronics
(SDD Detector, Pascal, Ambra)

Design of the final versions of CARLOS chip, CARLOS_rx board
INFN Bologna 2003 - Davide Falchieri
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