Politecnico di Torino
Dipartimento di Automatica e Informatica
http://www.testgroup.polito.it
Dependability for digital systems
Di Carlo Stefano
[email protected]
Pisa, Italy 25-27 Nov. 2002
DeSire & DeFINE Workshop
People
• Prof. Paolo Prinetto (Full Professor)
– Test Technology Technical Council (TTTC) chair of the IEEE
Computer Society
• Eng. Alfredo Benso (Researcher)
• Eng. Stefano Di Carlo (Assistant Researcher)
• Eng. Giorgio Di Natale (Assistant Researcher)
• Andrea Baldini, Luca Tagliaferri, Gianfranco Panico,
Ivano Solcia, Alberto Bosio (PhD Students)
• More than 15 thesis students
Pisa, Italy 25-27 Nov. 2002
DeSire & DeFINE Workshop
Test Group Scope
• Built In Self Test (BIST) and Design for
Testability (DfT)
• From core to system test
• Dependability and Fault tolerance w.r.t.:
– Hardware permanent faults
– Hardware transient faults (due to environmental
stresses)
• EDA tools developement
Pisa, Italy 25-27 Nov. 2002
DeSire & DeFINE Workshop
Test Group Scope: Technical
Diversification
Product Life Cycle
Field
Factory
Design
DSP
Memory
Processor
FPGA
Levels of
Integration
Technology
Pisa, Italy 25-27 Nov. 2002
DeSire & DeFINE Workshop
On going R&D funded projects
• ICT Boella: TEST D.O.C. Quality and dependability
of Complex SoC
• ASI (Italian Space Agency): Dependability of COTS
based systems
• MIUR (Italian Ministry of Research and University)
Legge 488: GRAAL: automatic generation highly
dependable memories
• EU VFP : EuNICE European Network for Initial and
Continuing Education in VLSI/SOC Testing using
remote ATE facilities
Pisa, Italy 25-27 Nov. 2002
DeSire & DeFINE Workshop
On going research contracts
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Ansaldo (Italy)
ASSET Inc. (USA)
CISCO (USA)
Italtel s.p.a. (Italy)
Magneti Marelli (Italy)
Siemens ICN (Italy)
Yogitech (Italy)
For a budget of ~150K €/year
Pisa, Italy 25-27 Nov. 2002
DeSire & DeFINE Workshop
Test Group & DeFINE
• Design of highly dependable digital
systems:
– Intelligent techniques to target
commercial components
– Cooperation of hardware and software
approaches to detect and correct for
faults during operation
– Low use of hardware and software
redundancy or non-standard process
technologies:
• Low performance degradation
• Low cost overhead
Pisa, Italy 25-27 Nov. 2002
DeSire & DeFINE Workshop