Modeling Flash Memories
for IC Designs
Luca Larcher
Università di Modena e Reggio Emilia
Reggio Emilia - Italy
[email protected]
Luca Larcher
September, the 14th
Università degli Studi
di Modena e Reggio Emilia
Flash memories


Flash memory market increased exponentially in the last
years
Flash are pervasive in every modern electronic system
Luca Larcher
September, the 14th
Università degli Studi
di Modena e Reggio Emilia
Floating-Gate (FG) transistor


The FG transistor is the basic element of NOR and NAND
Flash memories
The information bit is stored by transistor threshold voltage
(VT), which can be changed in a non-destructive way by
injecting/removing charge to/from FG
Control Gate
INTERPOLY OX.
Floating Gate
TUNNEL OX.
Drain
Source
P-substrate
Luca Larcher
September, the 14th
Università degli Studi
di Modena e Reggio Emilia
NOR Flash array
In a NOR array, a cell, i.e.
a FG transistor is identified
by a WL – BL cross
Single NOR Flash
= FG MOSFET
Sourcelines
G
Bitlines (BL)
Wordlines (WL)

S
D
Luca Larcher
September, the 14th
Università degli Studi
di Modena e Reggio Emilia
NAND Flash array
Bitlines

BSL
Select Transistors

NAND Flash cells
are organized in
strings
Each string is
comprised of
32/64 cells,
connected in
series
High density, i.e.
high capacity is
thus achieved
16 Wordlines

GSL
Luca Larcher
September, the 14th
Università degli Studi
di Modena e Reggio Emilia
Outline

Motivations

Floating Gate (FG) transistor model:


DC model and FG voltage calculation

Transient model

Program/erase current

Stress Induced Leakage Current, SILC
NOR and NAND Flash Spice-like models

Parameters and extraction procedure

Simulation results

Conclusions
Luca Larcher
September, the 14th
Università degli Studi
di Modena e Reggio Emilia
Motivations



Designing NAND and NOR Flash memories requires Spicelike circuit simulations, that need accurate compact
models to be effective
Flash memory cells are usually replaced with standard
MOS in industry circuit simulations
FG potential is usually calculated through the capacitive
coupling coefficient method, i= Ci/CT
VFG  CG VCG  DVD  SVS  BVB


Constant capacitive coupling coefficients leads to errors in
VFG calculation
Optimum models should be: Spice-like, compact, accurate,
usable in DC and transient conditions
Luca Larcher
September, the 14th
Università degli Studi
di Modena e Reggio Emilia
The FG transistor DC model
Control Gate
CPP
Floating Gate
VFG
Source
P-substrate
Body
Drain
CPP = interpoly dielectric capacitance
VFG = Floating Gate voltage
Luca Larcher
September, the 14th
Università degli Studi
di Modena e Reggio Emilia
VFG calculation
CG

FG
VFG
S
D
VFG is calculated by solving
the charge neutrality
equation at the FG node:
QMOS + QCPP = QP/E
B



QCPP = CPP(VFG-VCG)
QP/E = charge injected into the FG during program/erase
(constant in DC conditions)
QMOS = f(VFG,VS,VB,VD) is a the charge on the MOS gate, which is
a complex function of voltages, calculated by means of the MOS
model charge equations
Luca Larcher
September, the 14th
Università degli Studi
di Modena e Reggio Emilia
Solution of charge equation

The charge neutrality equation is an implicit equation in
VFG:
F(VFG) = QMOS(VFG) + QCPP(VFG) – QW/E = 0



No analytical solution due to the complex QMOS expression
Spice-like simulator solves it numerically through suitable
convergence algorithms
F is monotonic versus VFG for all bias combinations
(VCG,VS,VB,VD), assuring the uniqueness, i.e. the physical
meaning of the derived VFG solution
Luca Larcher
September, the 14th
Università degli Studi
di Modena e Reggio Emilia
The FG transistor transient model

Current sources (IW1, IW2, IW3) are included to model
program and erase currents, i.e. Fowler-Nordheim (FN)
and Channel Hot Electron (CHE) currents
Control Gate
CPP
Floating Gate
Iw1
Iw3
Iw2
Source
Drain
Body
Luca Larcher
September, the 14th
P-substrate
Università degli Studi
di Modena e Reggio Emilia
VFG
Fowler-Nordheim current sources

Current sources analytically modeling Fowler/Nordheim
currents allow reproducing program-erase and erase
operations of NAND and NOR Flash memories,
respectively.
 BFN 
IFN Fox   A T A F  exp  

 Fox 
2
FN ox

AT
AFN , BFN

FOX

Luca Larcher
September, the 14th
= area of the tunneling region
= Fowler-Nordheim physical coefficients
depending on the Si/SiO2 barrier
= electric field across the tunnel oxide
Università degli Studi
di Modena e Reggio Emilia
FOX calculation
FOX
V


FG
 VS,D,B   VFB  S  P
TOX
VFB = flat-band voltage
– S = surface potential drop at Si/SiO2 interface
– P = surface potential drop at poly-Si/SiO2 interface
To correctly evaluate S and P, poly depletion and
charge quantization effects are taken into account through
a self consistent model [1]
The so calculated FOX has been included in the FG model
through empirical formulas
–


[1] L. Larcher et al., “A new model of gate capacitance …”, IEEE Trans. Elect. Devices
Luca Larcher
September, the 14th
Università degli Studi
di Modena e Reggio Emilia
CHE current source
CHE and Channel Initiated Secondary ELectron (CHISEL)
currents can be modeled through simplified approaches
allowing modeling the high energy distribution of hot carriers

[2]
CHISEL
Gate
Source
CHE
e1
Impact Ionization
M4
e3
M3
h2,3
[2]
M2 M1
h2
e1,2
Drain
Body
L. Larcher, P.Pavan, “A New Analytical Model of Channel Hot Electron (CHE) and
CHannel Initiated Secondary ELectron (CHISEL) …,” MSM 2002, 2002, pp. 738-741.
Luca Larcher
September, the 14th
Università degli Studi
di Modena e Reggio Emilia
Stress Induced Leakage Current, SILC
SILC [3] is included through current sources allowing
simulating the threshold voltage degradation due to the aging
of the tunnel oxide induced by P/E cycles
SILC modeled assuming the inelastic Phonon Trap-Assisted
Tunneling (PTAT) as conduction mechanism


SiO2
cathode
Ep
[3]
L. Larcher et al., IEEE Trans.
Electr. Devices, Vol.48, N.2,
2001, pp.285-288.
Luca Larcher
September, the 14th
xT
tox
anode
Università degli Studi
di Modena e Reggio Emilia
NOR Flash model & parameters




The NOR Flash Spice-like model is the FG MOSFET model
Parameters of M1 are extracted applying the standard
MOSFET parameter extraction procedure to the dummy cell,
that is a cell with FG and CG short-circuited
Additional parameters
from SEM measurements
CG
and TCAD simulations :
FG-CG capacitance;
FG
parameters of current
sources
IW1
IW2
Practically, no additional
costs compared to a
S
D
M
1
standard MOSFET
Luca Larcher
September, the 14th
Università degli Studi
di Modena e Reggio Emilia
NAND Flash model & parameters

The NAND Flash memory string model is a sub-circuit
comprised of equivalent dummy cell MOSFETs, inter-poly
capacitances, coupling capacitances, P/E current sources
WL2
WL1
WLn
CFC
CFC
CFS
BLm+1
WLn
WL1
SSL CFS
CFFB
CFFB
CFS DSL
SL
BLm
CFL
Luca Larcher
September, the 14th
CFL
Università degli Studi
di Modena e Reggio Emilia
NAND Flash model & parameters -2



Coupling capacitances between FGs of adjacent cells, FCF
and CFFB, are additional parameters derived from SEM
measurements and TCAD simulations
Parameter of the equivalent MOSFET are extracted from
a string of dummy cells, paying attention to correctly
account for series resistance effects
Again, current sources can be inserted to account for
program/erase Fowler-Nordheim currents
SSL
SL
Luca Larcher
September, the 14th
WL1
WL15
WL32
DSL
BL
Università degli Studi
di Modena e Reggio Emilia
DC – NOR Flash: IDS-VCG
10-4
VSB (exp) 0..2 step 0.5V
10-5
I DS (A)
10-6
VSB= 0V
W=0.25 mm
L=0.375 mm
10-7
10-8
VSB= 2V
10-9
VDS= 0.1V
10-10
simulation
-11
10
2
3
4
5
6
7
VCG (V)
Luca Larcher
September, the 14th
Università degli Studi
di Modena e Reggio Emilia
DC – NOR Flash: IDS-VDS
25
simulation
VCG= 4 V
VB= 0 V
20
I DS (mA)
VCG= 3.75 V
15
VCG= 3.5 V
10
VCG= 3.25 V
5
VCG= 3 V
0
0
0.3
0.6
0.9
1.2
1.5
1.8
VDS (V)
Luca Larcher
September, the 14th
Università degli Studi
di Modena e Reggio Emilia
DC – NOR Flash: IDS-VCG
60
50
I D (mA)
40
30
20
W=0.16 mm
L=0.3 mm
simulation
VD (exp)
0.1 V
0.7 V
1.3 V
1.9 V
10
0
2
2.5
3
3.5
4
4.5
5
5.5
6
VCG (V)
Luca Larcher
September, the 14th
Università degli Studi
di Modena e Reggio Emilia
DC - NAND Flash: IDS-VCG
1.0E-06
cell #16 in the string
VD=0.1V
IDS [A]
1.0E-07
1.0E-08
VB=0V
VB=-1V
1.0E-09
VB=-2V
SIM
1.0E-10
-1.0
0.0
1.0
2.0
3.0
VCG [V]
Luca Larcher
September, the 14th
Università degli Studi
di Modena e Reggio Emilia
Erase – NOR Flash: VT - time
7
VG0(exp) -2.7..-4.7 step 1V
6
V T (V)
5
VG0= -4.7 V
VCG
4
3
Erase bias:
D float
VS=VB=8 V
VG,MAX
VG0= -2.7 V
2
1
VG0
simulation
0
0
0.1
Time
VB= VS= 8 V
0.2
0.3
0.4
Time (s)
Luca Larcher
September, the 14th
Università degli Studi
di Modena e Reggio Emilia
Erase – NOR Flash: VT - time
7
dV/dt (exp)= 12.5,20,25,30,35,50,60 V/s
simulation
6
V T (V)
5
4
dV/dt= 12.5V/s
3
2
1
0
0
dV/dt= 60 V/s
0.1
0.2
0.3
0.4
Time (s)
Luca Larcher
September, the 14th
Università degli Studi
di Modena e Reggio Emilia
Program – E2PROM Flash: VT
4
3
Lines: simulations
Symbols: measures
VT (V)
2
1
0.3
0
0.4
0.5
TRISE(m
s)
-1
0.6
12V VCG-ramp
VD=VB=0V
TRISE VS=0V
-2
-3
No free
parameter
to improve
the fitting
quality!!
0
0.1 0.2
0.3 0.4 0.5 0.6 0.7 0.8
0.9
1
Time (ms)
Luca Larcher
September, the 14th
Università degli Studi
di Modena e Reggio Emilia
Program – E2PROM Flash: tunnel current
60
ITUN (pA)
excellent fitting using real VCG
50 ramp!!
VVCG
ramp
D-ramp
Nominal
40
Real
TRISE
30
20
10
0
0.4
Lines: simulations
Symbols: measures
0.5
0.6
0.7
0.8
0.9
1.0
1.1
Time (ms)
Luca Larcher
September, the 14th
Università degli Studi
di Modena e Reggio Emilia
E2PROM Flash: retention simulation
NC = number
of P/E cycles
NC
4.7
E2PROM cell
left unbiased in
retention
10 - 1 - fresh
VT(V)
4.2
10
2
3.7
10
10
3.2
VT reduction
induced by
SILC, included
by some
current sources
3
4
NC= 105
2.7
0
1
Luca Larcher
September, the 14th
2
3
4
5 6
Years
7
8
9 10
Università degli Studi
di Modena e Reggio Emilia
Advantages & conclusions

This Flash memory modeling approach has several
advantages

The parameter extraction procedure is simple
it is similar to the one of a standard MOSFET and few
additional parameters are derived from SEM measurements
and TCAD simulations

The simulation time is comparable to MOSFET

VFG calculation procedure does NOT use capacitive
coupling coefficients
the VFG calculation is much more accurate compared to the
usual method considering capacitive coupling coefficients as
constants, which introduces errors
Luca Larcher
September, the 14th
Università degli Studi
di Modena e Reggio Emilia
Flash coupling coefficients: CG
CG
VB=-1V
VS=0V
0.72
0.70
0.68
0.66
0.64
9
8
66.75
55.63
44.5
33.38
22.
11.13
0
0
1
2
3
VCG
5
VFG  CG VCG  DVD  SVS  BVB
Luca Larcher
September, the 14th
4
VD
Università degli Studi
di Modena e Reggio Emilia
Advantages & conclusions -2





NOR and NAND Flash compact models are simply developed as
sub-circuit
DC, transient and reliability simulations of single devices and
circuits excellently reproduce measurements without free
parameters to improve the fitting quality
Easily scalable: scaling rules are taken into account in the
MOSFET model itself, and they do not affect the VFG calculation
Easily upgradeable: voltage and current sources can be
replaced/modified independently
Can be used for statistical analysis (effects of statistical
fluctuation of critical parameters, …)
Luca Larcher
September, the 14th
Università degli Studi
di Modena e Reggio Emilia
References
o






Paolo Pavan, Luca Larcher, Andrea Marmiroli, Floating Gate devices: Operation
and Compact Modeling, Kluwer Academic Publishers, 2004, 140 pp., ISBN 1-40207731-9
L. Larcher et al., Bias and W/L Dependence of Capacitive Coupling
Coefficients in Floating Gate Memory Cells, IEEE Trans. on Electron Devices,
Vol. 48(9), pp. 2081-2089, 2001.
L. Larcher et al., A New Compact DC Model of Floating Gate Memory Cells
Without Capacitive Coupling Coefficients, IEEE Trans. on Electron Devices,
Vol.49(2), pp. 301-307, 2002.
L. Larcher et al., A complete model of E2PROM memory cells for circuit
simulations, IEEE Trans. on CAD, Vol. 22(8), pp. 1072-1079, 2003.
L. Larcher and P. Pavan, Statistical simulations for Flash memory reliability
analysis and prediction, IEEE Trans. on Electron Device, Vol. 51(10), pp. 16361643, 2004.
Luca Larcher et al., Modeling NAND Flash memories for circuit simulations, IEEE
SISPAD, 2007
L. Larcher et al., Flash memories for SoC: an overview on system constraints and
technology issues, (invited paper) IEEE IWSoC2005, 2005.
Luca Larcher
September, the 14th
Università degli Studi
di Modena e Reggio Emilia