SL
U
RL
SL
LSI
Eneg
Clock
ShiftRegister1
Cneg
U
Module:
ShiftRegister4
4 of 5
February 4, 2003
U
RSI
I
Date:
Clock
ShiftRegister1
Eneg
Page:
Clock
RL
SL
Cneg
cominipm.dimi.uniud.it
Clock
RL
ShiftRegister1
LSI
LSI
SL
RSI
RSI
Eneg
I
Cneg
I
Site:
RL
RSI
Eneg
Cneg
Document: Serial To Parallel Converter
LSI
3
2
1
0
4
Designer: Marco Comini
I
RL
SL
LSI
RSI
I
Eneg
Clock
ShiftRegister1
Cneg
U
3
2
1
0
4
TKGate 1.6i
U
Q
Q
Module:
ShiftRegister1
1 of 5
February 4, 2003
C E
Date:
D
Page:
Clock
3
cominipm.dimi.uniud.it
0
Site:
2
Document: Serial To Parallel Converter
1
0
LSI
RSI
Designer: Marco Comini
RL
SL
I
Cneg
Eneg
U
TKGate 1.6i