US 20110310656Al
(19) United States
(12) Patent Application Publication (10) Pub. No.: US 2011/0310656 A1
(43) Pub. Date:
Kreupl et al.
(54)
MEMORY CELL WITH
RESISTANCE-SWITCHING LAYERS
INCLUDING BREAKDOWN LAYER
(76) Inventors:
Franz Kreupl, Munchen (DE);
Chu-Chen Fu, San Ramon, CA
(US); Yibo Nian, Milpitas, CA
(Us)
(21) Appl. No.:
(22)
Filed:
13/157,208
Jun. 9, 2011
Related US. Application Data
(60)
Provisional application No. 61/356,327, ?led on Jun.
(57)
US. Cl. .................... .. 365/148; 257/4; 257/E45.001
ABSTRACT
A memory device in a 3-D read and write memory includes
memory cells. Each memory cell includes a resistance
switching memory element (RSME) in series with a steering
element. The RSME has a resistance-switching layer, a con
ductive intermediate layer, and ?rst and second electrodes at
either end of the RSME. A breakdown layer is electrically
between, and in series with, the second electrode and the
intermediate layer. The breakdown layer maintains a resis
18, 2010, provisional application No. 61/467,936,
tance of at least about 1-10 MQ while in a conductive state. In
a set or reset operation of the memory cell, an ionic current
?led on Mar. 25, 2011.
?ows in the resistance-switching layers, contributing to a
Publication Classi?cation
(51)
(52)
Dec. 22, 2011
Int. Cl.
G11C 11/00
H01L 45/00
(2006.01)
(2006.01)
switching mechanism. An electron ?ow, which does not con
tribute to the switching mechanism, is reduced due to scatter
ing by the conductive intermediate layer, to avoid damage to
the steering element. Particular materials and combinations
of materials for the different layers of the RSME are provided.
5114
108
Patent Application Publication
Dec. 22, 2011 Sheet 1 0f 21
Fig. 1
US 2011/0310656 A1
f 100
108
102
130
133
135
132
134
104
106
144
142146
\113
Fig. 2A
100
5114
Patent Application Publication
Dec. 22, 2011 Sheet 2 0f 21
Fig. 2B
116
120
100
118
100
114
120
118
US 2011/0310656 A1
Patent Application Publication
Dec. 22, 2011 Sheet 3 0f 21
US 2011/0310656 A1
Fig. 3
300
308
/
row
decoder
O
322
(5}!)
E,
array
,
drivers
324
5
E <
>
g
_
C
O
O
0
O
‘
block
5 ‘
I
select
‘
'
326
memory array
302
A
A
A
<:-- 3
90mm‘
signals
Vcolumn
V
Vdriver
block
decoder
circuitry
select
312
314
316
column control circuitry 310
column
drgw
8. gels’s
sig as
System Control
Logic
330
l
host
address
signals
Patent Application Publication
Dec. 22, 2011 Sheet 4 0f 21
US 2011/0310656 A1
lreset
lset_|imit
Ia
0V
Vread Vreset
Vset
Vf
lresetA
lset_|imitA
lresetB
lset_|imitB
0v
|
I
VresetB VresetA
|
VsetB
|
|
VsetA VfA
> v
Patent Application Publication
Dec. 22, 2011 Sheet 5 0f 21
US 2011/0310656 A1
A
Flgl
lreset
.
_
_
_
_
_
_
_
_
_
_
_
_
|set_|imit
Set
- Ia
436
..|b
|
|
|
|
|
Vf
Vset
I
|
|
|
’
Vreset Vread
V
0V
I
M
Flg. 4D
lreset
.
.
.
.
.
.
.
.
.
_|Sit_?m_it______________
442
Set
Reset
440
446
444
l
|
I
|
|
Vreset
0V
|
Vset
Flg. 4 E
.'r.eS.et.
.
.
.
.
452
450
456
454
Vf
Vf
.
set
|
V
A'
|set_|imit
|
>
I
|
|
Vset
Reset
|
0V
Vreset
’ v
Patent Application Publication
Dec. 22, 2011 Sheet 6 0f 21
US 2011/0310656 A1
Fig. 5
Sense amp,
566
data
latch
/
I
0 amp
56,8
562‘\:|
Data bus (~2 V)
control
circuit, 564
553“
column
write
circuit, 560
decoder \ ~0v /
312 558
I
547“
Data
550 ’;>K 552 'JBK
549“
554 ’:>K 555 W‘ZK
k-559
"557
Patent Application Publication
US 2011/0310656 A1
Dec. 22, 2011 Sheet 7 0f 21
Fig. 6A
Fig. 68
Bit line contact
BLC
(BLC)
Adhesion layer
(AL1)
AU
Resistance-
RSME
switching memory
element (RSME)
Steering element
AL2
WLC
SE
(SE)
Adhesion layer
(AL2)
Word line contact
(WLC)
First electrode (E1)
First resistance
switching layer
(RSL1)
RSME
Intermediate layer
UL)
RSL2
Second electrode
(E2)
E1
RSL1
RSME
lL2
|L1
RSL2
E2
_
Flg. 6C
Patent Application Publication
US 2011/0310656 A1
Dec. 22, 2011 Sheet 8 0f 21
E1
RSL1
RSME
Fig. 6E
RS L2
RS L3
E2
Fig. 66
RSME
RSL1
lL
E1
NC
RSL2
E2
RSME
’—J——\
E1
AFC/DE
E2
Fig. 6H
Patent Application Publication
Dec. 22, 2011 Sheet 9 0f 21
US 2011/0310656 A1
E1
RSL1
IL
Breakdown RSL
E2
Fig. 6K1
Patent Application Publication
Dec. 22, 2011 Sheet 10 0f 21
US 2011/0310656 A1
#1
Fig. 6K2
Eb
i
|
Fig. 6K3
0v
3
E1
Breakdown RSL
IL
RSL1
E2
I
Flg. 6L
Patent Application Publication
Dec. 22, 2011 Sheet 11 0f 21
US 2011/0310656 A1
E1
RSL1 (type A)
RSME
6M
lL
RSL2 (type B)
E2
.
SE
.
.
.
|
......... ..
Fig. 78
Bit line
BLC (W or NiSi)
AL1 (TiN)
E1 (n+ Si)
RSL1 (MeOx)
Cap1 (TiOx)
IL (TiN)
Cap2 (TiOx)
RSL2 (MeOx)
E2 (n+ Si)
AL (TiN)
SE (Si diode)
AL2 (TiN)
WLC (W or NiSi)
Word line
I
Flg. 8
Patent Application Publication
Dec. 22, 2011 Sheet 12 0f 21
Flg. 9A
US 2011/0310656 A1
Hg. 95
E1
E1 (p+ SiC)
RSL1
RSL1
Cap1 (TiOx)
IL (p+ SiC)
IL (TiN)
RSL2
Cap2 (TiOx)
E2
RSL2
E2 (n+ Si)
Hg. 90
Evacuum
1___r
_
_
_
_
_
_
___
qx
EC
Al (4.28 eV)
"
4 QV_%TL Zn (4.33 eV)
k
/ W (4.55 eV)
_ Mo (4.60 eV)
~6.6-6.9 eV
Eg=3.26 eV
\
5 eV-\ Cu (4.65 eV)
\ Au(5.15eV)
Ni (5.10 eV)
E'-_--_-'
6eV
Pt (5.65 eV)
p+
SiC
_., _
_
_
_
_
_
_
Ferml level
_
_
7 ev_
EV
‘V
Y
Patent Application Publication
Dec. 22, 2011 Sheet 13 0f 21
US 2011/0310656 A1
Fig. 10A
Fig. 105
E1 (TiN)
E1 (TiN)
E1 (n+ Si)
RSL1 (MeOx)
Cap1 (TiOx)
RSL1 (MeOx)
Cap1 (TiOx)
IL (TiN)
IL (n+ Si)
RSL2 (MeOx)
Cap2 (TiOx)
Cap2 (TiOx)
RSL2 (MeOx)
E2 (TiN)
E2 (n+ Si)
Fig. 106
Fig. 10D
E1 (TiN)
E1 (TiN)
Cap1 (TiOx)
RSL1 (MeOx)
IL (n+ Si)
|L(TiN)
Cap2 (TiOx)
RSL2 (MeOx)
E2 (n+ Si)
E1 (n+ Si)
RSL1 (MeOx)
Cap1 (TiOx)
IL (TiN)
IL (n+ Si)
RSL2 (MeOx)
Cap2 (TiOx)
E2 (TiN)
Patent Application Publication
E1 (n+ sI)
RSL1 (MeOx)
Dec. 22, 2011 Sheet 14 0f 21
FIg.11A
Cap1 (TiOx)
IL (TIN)
E1 (n+ sI)
RSL1 (MeOx)
Cap1 (TiOx)
IL (TIN)
Fig.11B
Cap2 (TiOx)
Cap2 (TiOx)
RSL2 (MeOx)
RSL2 (MeOx)
TiOX
SiOx
Ti
E2 (n+ sI)
E2 (TIN)
E1 (n+ sI)
RSL1 (doped
E1 (n+ sI)
RSL1 (doped
MeOx)
Cap1 (TiOx)
US 2011/0310656 A1
Fig. 110
MeOx)
Cap1 (TiOx)
IL (TiN)
IL (TiN)
Cap2 (TiOx)
Cap2 (TiOx)
FIg. 11D
RSL2 (doped
RSL2 (doped
MeOx)
MeOx)
TiOX
SiOx
Ti
E2 (n+ sI)
E2 (TIN)
E1 (n+ Si)
RSL1 (type A
E1 (n+ sI)
Fig. 11E
RSL1
MeOx)
Cap1 (TiOx)
(type A MeOx)
IL (TIN)
IL (TIN)
Cap2 (TiOx)
Cap2 (TiOx)
RSL2 (type B,
RSL2 (type B,
MeOx)
MeOx)
SiOX
TiOX
Ti
E2 (n+ Si)
Cap1 (TiOx)
E2 (TiN)
FIg.11F
Patent Application Publication
Dec. 22, 2011 Sheet 15 0f 21
US 2011/0310656 A1
Fig. 12
E01
EE2
+> distance
E1
RSL1
IL
RSL2
E2
Patent Application Publication
Dec. 22, 2011 Sheet 16 0f 21
US 2011/0310656 A1
Fig. 13
3-5 nm
OV
EL
RSL
ER
Patent Application Publication
EL=O V
Dec. 22, 2011 Sheet 17 0f 21
RSL (HfO2)
OOOOO
O O OOOOO
US 2011/0310656 A1
ER=5 V
Fig. 14A
O O OOOOO
EL=O V
RSL (HfO2)
OOOOO
O O OOOOO
O O OOOOO
RSL (HfO2)
EL=O V
ER=5 V
OO
Fig. 148
ER=5 V
OOOOO
OOOOO OOO
Fig. 140
O O OOOOO
RSL (HfO2)
EL=O V
ER=5 V
OOOOO
OO
CO... OOO
OOOOO
OOO
Fig. 14D
Patent Application Publication
Dec. 22, 2011 Sheet 18 0f 21
E A}
EC2
US 2011/0310656 A1
_
_ ................................................ .
Fig. 14E
EC2
_ .
.
.
.
.
.
_
electrons‘;
Fig. 14F
5V
EER
EA
Ec2 —
EER
Patent Application Publication
Dec. 22, 2011 Sheet 19 0f 21
RSL1 (HfO2)
US 2011/0310656 A1
ER:_5 V
EL=°V00oooooOO
‘000000000
F.
'9'
15A
‘000000
RSL (HfO2)
ER_ 7 V
EL=°VoooooooOO
000000000
Fig.15B
.OOOOOO
RSL (HfO2)
ER_ 9 V
EL=°V0ooooooOO
00000000
‘000000
F150
'9'
Scarica

Memory Cell With Resistance-Switching Layers Including