High-Level Optimization of
Built-In Self Test for Analog to
Digital Converters
Daniela De Venuto
(Politecnico di Bari, Italy)
Leonardo Maria Reyneri
(Politecnico di Torino, Italy)
17/5/06
1
ADC testing methods
 Hystogram test
 Servo-loop test
 FFT test
 But none of them is appropriate for Built-
In Self Test
  Polynomial Fitting Technique (S.
Sunter, N. Nagi)
06/24/05
MELECON 06 - D. De Venuto, L.M. Reyneri
3
Polynomial fitting technique (1)
 A smoothed staircase signal is generated as
ADC test input, spanning the full input range
06/24/05
MELECON 06 - D. De Venuto, L.M. Reyneri
4
Polynomial fitting technique (1)
 The output of DAC is sampled at a constant rate.
 The coefficients of the best-fitting polynomial are easily
calculated, even on-chip, by four sindromes
B0  S0  S1  S2  S3
B1  S0  S1  S2  S3
B2  S0  S1  S2  S3
B3  S0  3S1  3S2  S3
Obtained by accumulating and summing (Si, i=0…3)
samples in four equal intervals at the ADC output.
06/24/05
MELECON 06 - D. De Venuto, L.M. Reyneri
4
Polynomial fitting technique (2)
 Once the four syndromes are known a
subset of specifications: offset, gain, HD2,
HD3 can be evaluated by simple
computation
4B1
gain @
Nr
06/24/05
IMSTW 05 - D. De Venuto
F. Dell'Olio, L.M. Reyneri
6
Optimization of polynomial fitting
 Smoothed staircase can easily be generated by
properly low-pass filtering a PWM signal with a
time-varying duty-cycle
 PWM signal must be generated by an ad-hoc
digital circuit  VHDL  FPGA,ASIC
 VHDL simulations are time consuming
 High level design and simulation allow an
accurate (down to -100dB) evaluation of the
performance
06/24/05
MELECON 06 - D. De Venuto, L.M. Reyneri
4
Optimization of polynomial fitting
 A large number of system-level simulations are
required to assess the performance of the
proposed technique and to optimize it.
 In particular:
– Effects of PWM frequency
– Effects of PWM low-pass filter
– Effects of number of accumulated samples (test
time)
– Effects of ADC and filter noise
– Effects of high-pass filters
– Other effects...
06/24/05
MELECON 06 - D. De Venuto, L.M. Reyneri
4
Optimization of polynomial fitting
 Such simulations cannot be done:
– With VHDL simulators (too time consuming; no analog model of
ADC, etc.)
– With SPICE simulator (similar problems)
– With SImulink (no model for digital circuits)
  we have therefore used CodeSimulink, a commercial
add-on for Simulink aimed at high-level HW/SW/analog
cosimulation and codesign
  straightforward description; accurate models of ADC;
automatically generates VHDL for digital subsystem
06/24/05
MELECON 06 - D. De Venuto, L.M. Reyneri
4
Implementing the technique
Block scheme of the testing system
DUT
The digital parts of the system are implemented
by using an FPGA which can be programmed
by using the tool CodeSimulink
06/24/05
IMSTW 05 - D. De Venuto
Dell'Olio, L.M. Reyneri
F.
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CodeSimulink Model
06/24/05
IMSTW 05 - D. De Venuto
Dell'Olio, L.M. Reyneri
F.
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Simulations and
measurements
We performed:
– simulations on ideal Nyquist ADC;
– simulations on ideal ΣΔ ADC;
 to identify the limits of the method and
therefore the discriminiation capabilities
– simulations on real ΣΔ ADC (PCM3002);
– measurements on real ΣΔ ADC (PCM3002):
 to evaluate the accuracy of the method
06/24/05
IMSTW 05 - D. De Venuto
F. Dell'Olio, L.M. Reyneri
13
What are we looking for?
The working principle
of the PWM-based
generator is such that
the actual “staircase”
suffers from the
presence of around
15mVpp ripple
The low-pass filter cannot remove the ripple, which may affect
the samples at the output of ADC.
The PWM signal is synchronized with ADC sampling, therefore
the ripple impact is definitely reduced, but not cancelled.
Effects of number of samples
X = Nyquist ADC
o = ΣΔ ADC
The method is
more accurate
on ΣΔ ADC and
independent on
N
The method on
Nyquist ADC is
dependent on N
06/24/05
IMSTW 05 - D. De Venuto
F. Dell'Olio, L.M. Reyneri
16
Effects of PWM phase shift
X = Nyquist ADC
06/24/05
o = ΣΔ ADC
IMSTW 05 - D. De Venuto
F. Dell'Olio, L.M. Reyneri
17
Effects of input high-pass filter
X = Nyquist ADC
o = ΣΔ ADC
Cutoff
freqency
above
0.6Hz
(Fs/65000)
significantly
affects both
ADC’s types
06/24/05
IMSTW 05 - D. De Venuto
F. Dell'Olio, L.M. Reyneri
20
Measurements on ΣΔ ADC
x = measurements
06/24/05
o = simulations
IMSTW 05 - D. De Venuto
L.M. Reyneri
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Simulations summary
More details on results in
D. De Venuto, F. Dell’Olio, L.M. Reyneri,
``Optimization of FPGA based test strategy for high
resolution ADC’’, in Proc. Of IMSTW 2005, Cannes
(F), 2005.
06/24/05
IMSTW 05 - D. De Venuto
F. Dell'Olio, L.M. Reyneri
22
Implementation
06/24/05
FPGA: Altera EP1K50
ADC: Burr-Brown PCM 3002
(Double channel CODEC 16/20 bit SΔ)
IMSTW 05 - D. De OPAMP:
Venuto
TL082
L.M. Reyneri
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Conclusions





06/24/05
The tested technique has measured a subset of
specifications parameters with an accuracy of 8590dB, for a high resolution ADC production test
Codesimulink is useful to design, optimize and
implement the technique (both FPGA and ASIC)
The system has been automatically compilied to an
FPGA (Altera 10K50)
Measurements showed perfect agreement with the
hybrid model
Work in progress: we are investigating the
possibility of a fully integrated solution of the test
strategy
IMSTW 05 - D. De Venuto
F. Dell'Olio, L.M. Reyneri
28