Design of ASIP Architectures for Image Processing in CMOS VLSI Technologies *S. Saponara, *L. Fanucci, *P. Terreni, S. Marsi, G. Ramponi *Dip. Ingegneria della Informazione - Università di Pisa Dip. Elettrotecnica, Elettronica, Informatica – Università di Trieste NEWCOM: NoE Wireless Communications Riunione Annuale GE 2006 Ischia, 21-23 giugno 2006 The Retinex Non Linear Filtering Class Y R I Problem: correcting images acquired in bad lighting conditions and emphasizing the details Applications: Consumer electronics, Medical imaging, Surveillance systems, Assisted drive systems State of art: Real time processing based on DSP (Nasa Langley Lab) Riunione Annuale GE 2006 Ischia, 21-23 giugno 2006 Design of Retinex-like Filters Algorithmic design: Non linear filters (inspired by the Human Visual System behaviour) with optimal performance – complexity trade-off vs. state-of-art Challenge: Reducing implementation cost (area, power), real-time processing, keeping the flexibility of the SW layer within the specific filtering class (r ) I_in 1 1 e blog r β R / 1 2 Rmod X Contrast enhnance RRF Luminance Estimation Y Luminance Correction Ymod I_out Linear Stretch y 1 255 y ( y) 255 255 Riunione Annuale GE 2006 Ischia, 21-23 giugno 2006 Solution: the ASIP Design Approach ASIPs SW Design ASICs HW Design Log Physically Optimized ICs 105 . . . 106 Digital Signal Processors Log P ower consumption Log Flexibility General Purpose Processors P erformance 103 . . . 104 Riunione Annuale GE 2006 Ischia, 21-23 giugno 2006 The ASIP Design Flow Automatic generation: LISA processor design - HDL code - C Compiler - Simulator - Debugger RTL automatically generated Gate-level synthesis Riunione Annuale GE 2006 Ischia, 21-23 giugno 2006 Designed VLSI architecture 7-stage pipeline: Fetch, Instruction Decode plus 5 execution stages 42 instructions (32-bit) 14-bit fixed point arithmetic LUT (ROM)-based realization of non linear operators: By-pass mechanism to avoid pipeline stall Riunione Annuale GE 2006 Ischia, 21-23 giugno 2006 ASIP vs. DSP and HW Dedicated Designs Target technology: 180 nm CMOS standard-cells 1.8 V Two man-month for both ASIP (LISA) and dedicated HDL designs ASIP vs. Dedicated (semi-custom flow) Same algorithmic quality of the dedicated HW design Increased complexity (area, power) x 1.6 Higher flexibility due to the SW layer ASIP vs. DSP (Nasa Langley lab) Reduced power cost by one order of magnitude Same flexibility for the Retinex filtering class Riunione Annuale GE 2006 Ischia, 21-23 giugno 2006
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