Banco
Banco
Registri
Registri
ADD | dest>,
SUB | MULT
DIV 1>, <Reg sorg 2>
C.S.
<Regs
<Reg |sorg
Example
instruction
Instruction Name
LHI | LLI
Meaning (RTL Language)
ADD R1, R2, R3
Add
Regs[R1] <- Regs[R2]+Regs[R3]
ADDI R1, R2, #3
Add immediate
Regs[R1] <- Regs[R2] + 3
LHI R1, #42
Load high immediate
Regs[R1] <- 42##016
SLLI R1, R2, #5
Shift left logical
immediate
Regs[R1] <- Regs[R2] << 5
SLT R1, R2, R3
Set less than
if (Regs[R2] < Regs[R3]) Regs[R1] <- 1
else Regs[R1] <- 0
4
Example
instruction
Meaning(RTL Language)
Instruction name
C.S.
<Regs
dest>,
immediato
(
<Reg
sorg>
)
LW R1,30(R2)
Load word
Regs[R1] <- Mem[30+Regs[R2]]
32
MemoriaLoad word
LW R1,1000(R0)
LB R1,40(R3)
Load byte
Esterna Load byte
LBU R1,40(R3)
LH R1,40(R3)
unsigned
Load half word
Regs[R1] <-32Mem[1000+0] ; Register R0 always contains 0
Regs[R1]
Banco
Registri
<-32 (Mem[40+Regs[R3]]0)24##Mem[40+Regs[R3]]
Regs[R1] <-32 024 ## Mem[40+Regs[R3]]
Regs[R1] <-32 (Mem[40+Regs[R3]]0)16 ## Mem[40+Regs[R3]] ##
Mem[41+Regs[R3]]
LF F0,50(R3)
Load float
Regs[F0] <- Mem[50+Regs[R3]]
C.S.
immediato
( <Reg dest>
), <Regs sorg>
32
LD FO,50(R2)
Load double
BancoStore word
SF 40(R3),F0
Store float
Registri
SW 500(R4),R3
Regs[F0] ##Regs[F1] <-64Mem[50+Regs[R2]]
Memoria
Mem[500+Regs[R4]] <-32Regs[R3]
Mem[40+Regs[R3]] <-32Regs[F0]
Esterna
SD 40(R3),F0
Store double
Mem[40+Regs[R3]] <-32Regs[F0];
Mem[44+Regs[R3]] <-32Regs[F1]
SH 502(R2),R3
Store half
Mem[502+Regs[R2]] <-16Regs[R3]16..31
SB 41(R3),R2
Store byte
Mem[41+Regs[R3]] <-8Regs[R2]24..31
5
Altero il contenuto del registro speciale PC che contiene
l’indirizzo in memoria programmi dell’istruzione corrente
Example
Instruction
J
name
JAL name
Instruction
name
Jump
Jump and link
Meaning (RTL Language)
PC <- name;
<= name< ((PC+4)+225)
((PC+4)-225)
Regs[R31] <- PC+4; PC <- name;
((PC+4)-225)<= name <((PC+4)+225)
<Regs dest> = PC
JALR
R2
Jump and link register
Regs[R31] <- PC+4;
PC <- Regs[R2]
JR
R3
Jump register
PC <- Regs[R3]
BEQZ R4, name
Branch equal zero
if (Regs[R4] == 0) PC <- name;
((PC+4)-215)<= name <((PC+4)+215)
BNEZ R4, name
Branch not equal zero
if (Regs[R4] != 0) PC <- name;
((PC+4)-215)<= name <((PC+4)+215)
6
Somma Vettoriale di due vettori A e B a n componenti int 32bits: C = A + B
- a, b, c sono i rispettivi indirizzi in memoria delle prime componenti vettoriali (int 32bits)
- tali vettori sono memorizzati in memoria con componenti sequenziali
Language C++
For (k=0; k<n; k++)
C[k] = A[k] + B[k];
C[k] = A[k] + B[k];
LW R1, a(R4)
LW R2, b(R4)
ADD R3,R1,R2
SW c(R4),R3
R1 <- Mem [R4+a]
R2 <- Mem [R4+b]
R3 <- R1 + R2
Mem [c+R4] <- R3
dove R4 = 0, 4, 8, 12 …, (4xn)
7
Somma Vettoriale di due vettori A e B a n componenti int 32bits: C = A + B
- a, b, c sono i rispettivi indirizzi in memoria delle prime componenti vettoriali (int 32bits)
- tali vettori sono memorizzati in memoria con componenti sequenziali
Language C++
For (k=0; k<n; k++)
C[k] = A[k] + B[k];
Istruzione precedente
LW R5, addr_n(R0)
SUB R4,R4,R4
label2: SLT R12,R4,R5
BEQZ R12,label1
carico il num “n x 4” in R5
azzero R4
if R4<R5 then R12=1 else R12=0
salta a label1 (+6x4) se R12=0
LW R1, a(R4)
LW R2, b(R4)
ADD R3,R1,R2
SW c(R4),R3
ADDI R4,R4,#4
J label2
label1: Istruzione successiva
Branch
Branch
incremento R4 di 4 byte
salta a label2(-8x4)
8