Universität Dortmund
Alma Mater Studiorum
Facoltà di Ingegneria, Bologna
Microcontrollers Interfaces
& Orcad
Marco Benocci, PhD
[email protected]
Marco Benocci , PhD – Microcontroller Interfaces – MPHS 2010/2011
- 1-
Universität Dortmund
Microcontrollers Interfaces
Alma Mater Studiorum
Facoltà di Ingegneria, Bologna
Embedded
“specialized processor targeted for a specific application”
o Signal re-sampling
o Signal generation:
• Periodic:
Cosinusoidal, Sinusoidal, Square, Rectangular, Saw tooth, Dirac seq.
• Non-periodic:
Noise, Ramp, Step, Dirac.
o Operators : Multiplication, Division, Sine, Cosine, Arc sine, Arc cosine, Absolute,
Square root, Natural logarithm, Binary logarithm or base 2 logarithm, Common
logarithm or base 10 logarithm, Exponential, Power, Random
o Windowing : Bartlett, Blackman, Hamming, Gauss, Hann, Kaiser, Welch
o Vectors: Power, Minimum, Maximum, Negate, Zero padding, Copy, Partial
Convolution, Convolution
o Filtering: FIR, least mean square, interpolation, IIR
o Transforms (Complex Fast Fourier Transform, Complex inverse Fast Fourier
Transform, Real to complex Fast Fourier Transform)
o IMA/DVI ADPCM
 Signal processing: math library.
 Real-time nature: latency, scheduling.
 Portability: lifetimey constraint (specially when battery-driven).
Photo: http://www.geekzone.co.nz
Marco Benocci , PhD – Microcontroller Interfaces – MPHS 2010/2011
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Universität Dortmund
Digital Processor:
general VS special purpose
Alma Mater Studiorum
Facoltà di Ingegneria, Bologna
Microprocessor (Central Processing Unit, CPU)
• First design in late-1960s. MP944 implemented the F-14A Central Air
Data Computer. Intel 4004 in 1971.
• General purpose (i.e. Intel Core, PowerPC).
• Features: ALU + sequencer + register (no memory or peripherals). Three
basic tasks: perform mathematical operations, move data between memory
locations and follow sets of instructions.
• The job of starting up the computer specifically involves the bootstrap
loader.
• The assembler translates semantic instructions developed by designers into
a language the CPU can use.
Microcontroller (MCU)
• The microcontroller is the integration of a number of useful functions into
a single IC package specialized form of microprocessor designed to be selfsufficient and cost-effective.
• Texas Instruments TMS1802 single-chip (4-bit) calculator device was
designed in 1971.
• Features: processor + data/program memory + digital IO.
• Application areas: automobiles, office machines, toys, and appliances.
Marco Benocci , PhD – Microcontroller Interfaces – MPHS 2010/2011
- 3-
Universität Dortmund
Focus on MCU
Alma Mater Studiorum
Facoltà di Ingegneria, Bologna
Performance Metrics:
• Low Power consumptions: Harvester needs less than 1uW
i.e. Atmel PicoPower (165μA/MHz).
• Cheap Price: consumer products.
i.e. MC9S08QG4 costs less than 1$ featuring 4 KB FLASH, 256 B RAM.
n.b. the package influences the final price due to the soldering.
• Easiness of integration: number and kind of Interfaces
i.e. STM32 (ARM Cortex M-3) provides USB Host, I2C, SPI, Ethernet, SDIO, CAN.
• High computational power: MIPS (Million of Instructions Per Seconds)
i.e. ARM Cortex A-8: 2,000 MIPS @ 1.0 GHz.
CORTEX
• ARM Cortex family is a complete processor core that provides a
standard CPU and system architecture.
• Three main profiles: A profile for high end applications, R for real
time and M for cost-sensitive and microcontroller applications.
• The Cortex-M3 provides a standardised microcontroller core
which goes beyond the CPU to provide the entire heart of a
microcontroller (including the interrupt system, SysTick timer,
debug system and memory map).
Marco Benocci , PhD – Microcontroller Interfaces – MPHS 2010/2011
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Universität Dortmund
Interfaces: policies
Alma Mater Studiorum
Facoltà di Ingegneria, Bologna
Visions
Transfert Modalities
 Real-time behavior
 Efficient, economical
• FIFO Buffer:
i.e. centralized power supply
 Bandwidth and communication delay
Inverse relation between volume and urgency
 Electrical robustness
Single-ended vs. differential signals
 Fault tolerance
Error detecting & error correcting bus protocols
temporarily store acquired data
• Interrupts:
the slowest but most common
method
• DMA (Direct Memory Access):
is a system whereby samples
are automatically stored in
system memory while the
processor does something else
 Maintainability
 Diagnosability
 Security & Safety
Error detecting and error correcting bus protocols
 Privacy
Encryption, virtually private
Marco Benocci , PhD – Microcontroller Interfaces – MPHS 2010/2011
- 5-
Universität Dortmund
Interfaces: signal acquisition
Alma Mater Studiorum
Facoltà di Ingegneria, Bologna
Data acquisition
system components:
Analog
• Analog To Digital Converter (ADC)
• Digital To Analog Converter (DAC)
•…
Digital
Signal Conditioning
Sensors and Actuator
IEEE1451
Subsistem Control
Storage
Connectivity
Data Streaming






 Asynch Memory
 ATAPI/Serial ATA
 Flash Storage Card
 SDRAM/DDR
 USB
 PCI
 IEEE 802.3 (Ethernet)
 IEEE 802.11 a/b7g (WiFi)
 IEEE 802.15 (WPAN)
 IEEE 1394 (Firewire)
 Asynchronous Memory
 Flash Storage Card
 Low Speed Serial Interfaces
 USB 2.0 Full Speed (12Mbps)
 10BaseT Ethernet
 IEEE 802.11b
 Synch Serial Audio/Data Ports
 Host Interface
 IEEE 802.11a/g
 100BaseT Ehternet
 USB 2.0 High Speed (480Mbps)
 IEEE 1394 (Firewire)
 Parallel Video/Data Ports
 Gigabit Ethernet
 PCI/ PCI Express
Low speed serial interfaces
Programmable Timers
GPIO
Real time clock
Watchdog Timer
Host Interface
Marco Benocci , PhD – Microcontroller Interfaces – MPHS 2010/2011
- 6-
Universität Dortmund
IEEE 1451
Alma Mater Studiorum
Facoltà di Ingegneria, Bologna
• The IEEE 1451 standard defines the
architecture that achieve to the sensors,
instruments and systems to work together with
relative ease.
• The IEEE 1451 vision underlines the change of
the computer role: the intelligence is distributed
over the network. The innovative concept of
Smart sensor aims to: move intelligence closer to
the point of measurement/control; create
confluence of transducers, computation and
communication towards common goal; make
sensor cost effective to integrate/maintain
distributed systems.
A TIM contains:
• from 1 to 255 transducers (can be a mix of
sensors and actuators);
• signal conditioning and processing
electronics;
• address logic (or microprocessor) to
implement a standardized Transducer
Interface (wired or wireless) defined by
IEEE 1451.X (.2, .3, .5, .6, ) between the
TIM and NCAP;
• a TEDS.
A NCAP integrates:
• a neutral smart transducer object and data
models that allow NCAP to communicate
sensor data and information to any network;
• NCAP to NCAP communications (defined
by IEEE 1451.1);
• application programming interfaces (API)
and a common set to access transducers
from a network (defined by IEEE 1451.0).
Marco Benocci , PhD – Microcontroller Interfaces – MPHS 2010/2011
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Universität Dortmund
IEEE 1451.2: Smart Sensor
Alma Mater Studiorum
Facoltà di Ingegneria, Bologna
Smart sensors is a transducer or an actuator easy to install, maintain, modify and upgrade.
• Integration of extensible Transducer Electronic Data Sheet (TEDS): a memory area inside the
sensor where sensor identification information, calibration data, measurement range are stored.
• Simplify the data exchange over the network (standard engineering units).
• Self-identification, self-diagnostic .
• Time aware’ for time stamping and correlation: Triggering and control model defines how
channels are accessed.
Marco Benocci , PhD – Microcontroller Interfaces – MPHS 2010/2011
- 8-
Universität Dortmund
Sensors: Classification
Alma Mater Studiorum
Facoltà di Ingegneria, Bologna
• The physics of their operation.
One physical principle can be used to measure many different phenomena.
e.g. piezoelectric effect can measure force, flexure, acceleration, heat, and acoustic vibrations.
• The particular phenomenon they measure.
One phenomenon can be measured by many physical principles.
e.g. sound waves can be measured by the piezoelectric effect, capacitance, electromagnetic field effects, and
changes in resistance.
• By a particular application.
e.g. one could group all sensors together that can be used to measure distance.
• Active VS passive.
Passive: the physical phenomena observed modifies some electrical characteristics of the sensor that can be
observed supply external power (e.g. RFID).
Self-generating sensor: the power is absorbed by the observed physical phenomena and transform in electric
power in output (e.g. RFID & Sensing).
• Energy.
Middelhoek’s classification energy domain such as electrical, thermanl, radiation, nechanical, magnetic, (bio)chemical.
• Technology.
e.g. MEMS
Marco Benocci , PhD – Microcontroller Interfaces – MPHS 2010/2011
- 9-
Universität Dortmund
Sensors: Calibration
Alma Mater Studiorum
Facoltà di Ingegneria, Bologna
• FSO (Full Scale Output)
Upper – Lower [endpoint of output]
• Calibration
Relationship between sensor output e applied physical input
Mechanical
Misalignements
(Factory)
• Error
Measured value – true value [% of FSO]
• Offset
Sensor output for zero applied input
• Hysteresis
Max [value approached with decreasing input - value approached with increasing input]
• Sensitivity
Max deviation of calibration point from straight line [% of FSO]
• Accuracy
Max deviation of calibration point from straight line [% of FSO]
• Repeatability
Max deviation of calibration point from straight line [% of FSO]
Saturation
FS
Bias Drift
• Resolution
Smallest change in the physical variable that results in a detectable change in the sensor output
• Frequency response
Change with frequency of out/in magnitude ratio and phase difference for sinusoidally varying input
• Cross-sensitivity
Sensitivity of sensor of a variable than the physical quantity under measurement
• Stability
Ability of sensor to reproduce output for identical input and condition over time
Bias
Non
Linearity
Vout
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Universität Dortmund
Sensors: Signals
Alma Mater Studiorum
Facoltà di Ingegneria, Bologna
Nature
Time interval definition (t0, t0+t)
• continuous-time, continuous-valued (real)
• discrete-time, continuous-valued (sampled)
• continuous-time, discrete-valued (quantified)
• discrete-time, discrete-valued (numeric)
Real
Sampled
Quantified
Numeric
"Conditioning" of a signal basically means to
manipulate a signal in such a way that it meets the
requirements of the next stage for further processing.
 translate the sensors output to a selected voltage
 modifying the sensors dynamic range to maximize
Features
(Time interval definition [t0, t0+t])
 the accuracy of the data acquisition system
 removing unwanted signals
 limiting the sensor's spectrum
Signal “Nature” to Voltage Convertion
• Current to Voltage
• Resistance to Voltage
• Signal Energy to Voltage
• Capacitance to Voltage

Peak-Peak:

Peak value (minus):

Peak value (plus):

Mean:

RMS:
Marco Benocci , PhD – Microcontroller Interfaces – MPHS 2010/2011
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Universität Dortmund
Conditioning the FSR
Alma Mater Studiorum
Facoltà di Ingegneria, Bologna
FSR – Force Sensor Resistor
Resistance to Voltage
Force sensing resistors use the electrical property
of resistance to measure the force (or pressure)
applied to a sensor.
FSR
Inseguitore
(Av=1)
Thresholding  Hardware Interrupt generation
If the sensor's voltage is greater than the threshold, the output of
the circuit is maximum (typically 5V).
FSR
If the sensor's output is less than the threshold, the output of the
circuit is minimum (usually 0V).
Marco Benocci , PhD – Microcontroller Interfaces – MPHS 2010/2011
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Universität Dortmund
ADC
Alma Mater Studiorum
Facoltà di Ingegneria, Bologna
The analog and continuous time signals
measured by the sensor and modified by the
signal conditioning circuitry must converted into
the form a computer can understand.
1.5
1
Aliasing
0.5
Impossible to reconstruct fast signals after slow
sampling: multiple fast signals share same
sampled sequence (mind Harry Nyquist)
0
-0.5
-1
-1.5
Example: Signal: 5.6 Hz; Sampling: 9 Hz
Sample and hold circuitry
• The ADC must have a stable signal in order to accurately perform
a conversion: the sample and hold circuitry take a snapshot of the
sensor signal and hold the value.
•The switch connects the capacitor to the signal conditioning circuit
once every sample period.
Equivalent circuit for the sample and hold
•The capacitor then holds the voltage value measured until a new
sample is acquired.
Marco Benocci , PhD – Microcontroller Interfaces – MPHS 2010/2011
- 13 -
Universität Dortmund
ADC Architectures
Alma Mater Studiorum
Facoltà di Ingegneria, Bologna
There are many different ADC architectures:
 Successive Approximation (SAR);
 Sigma Delta (SD or );
 Slope or Dual Slope;
 Pipeline;
 Flash...as in quick, not memory.
Marco Benocci , PhD – Microcontroller Interfaces – MPHS 2010/2011
14
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Universität Dortmund
ADC in MSP430 (SAR 12bit)
Alma Mater Studiorum
Facoltà di Ingegneria, Bologna
Vin
Key idea: binary search
Set MSB='1‘
(if too large: reset MSB)
Set MSB-1='1‘ (if too large: reset MSB-1)
e.g. successive approximation
V-
V
N = (approximated - real signal) called quantization noise.
1100
Vin
1011
Quantum
1010
Resolution12bit
1000
V-
Features:
• resolution (i.e. 12bit)
e.g. quantization noise for sine wave
• maximum conversion rate (i.e. 200 ksps)
• sampling periods controller (i.e. software or timers)
• on-chip reference voltage generation (i.e. 1.5 V or 2.5 V)
• individually configurable external input channels
• single-channel, repeat-single-channel, sequence, and repeat-sequence conversion modes
• number of storage registers
• cross-talking
Marco Benocci , PhD – Microcontroller Interfaces – MPHS 2010/2011
t
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Universität Dortmund
DAC
Alma Mater Studiorum
Facoltà di Ingegneria, Bologna
PWM signals are often used to create analog signals
in embedded applications.
We create a sine wave level with pulse-width
modulated (PWM) signals from Timer_B
Marco Benocci , PhD – Microcontroller Interfaces – MPHS 2010/2011
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Universität Dortmund
UART
Alma Mater Studiorum
Facoltà di Ingegneria, Bologna
UART (universal asynchronous receiver / transmitter) , Goldon Bell 1971 (?)
 Asynchronous.
 UART controller is the key component of the serial communications subsystem of a computer. The UART
takes bytes of data and transmits the individual bits in a sequential fashion.
 7- or 8-bit data with odd, even, or non-parity
 LSB-first data transmit and receive
 Simple compatibility with RS232
 The start bit is always a 0 (logic low), which is also called a space.
 Cheap: serial transmission of digital information (bits) through a single wire or other medium is much more
cost.f
 Standard baudrate: 2400, 19200, 57600,115200, 921600…
Focus: reliability
 The UART usually does not directly generate or receive the external signals used between different items of
equipment. Typically, separate interface devices are used to convert the logic level signals of the UART to and
from the external signaling levels.
than parallel transmission through multiple wires.
CTS
DCD
DSR
DTR
RTS
RI
Clear to
Send
Data
Carrier
Detect
Data Set
Ready
Data
Terminal
Ready
Request
To Send
This line indicates that the Modem is ready to exchange data.
When the modem detects a "Carrier" from the modem at the other
end of the phone line, this Line becomes active.
This tells the UART that the modem is ready to establish a link.
This is the opposite to DSR. This tells the Modem that the UART is
ready to link.
This line informs the Modem that the UART is ready to exchange
data.
Ring
Goes active when modem detects a ringing signal from the PSTN.
Indicator
Marco Benocci , PhD – Microcontroller Interfaces – MPHS 2010/2011
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Universität Dortmund
UART
Alma Mater Studiorum
Facoltà di Ingegneria, Bologna
Pros
• Asynchronous serial devices, such as UARTs, do not share a common clock.
• Compatible with RS232C
Cons
• Each device has its own, local clock.
• The devices must operate at exactly the same frequency (baudrate automatical
detection).
• Logic (within the UART) is required to detect the phase of the transmitted
data and phase lock the receiver’s clock to this.
DB-25
RS232C
• An old standard (1960), originally intended for connecting computer
equipment (computers or terminals, referred to as DTE) to communication
equipment (DCE).
• RS232C is are commonly used in conjunction with UART because they share
the same protocol.
• RS232 Voltages are +5..+25V for a logic 0, and -5V..-25V for a logic 1
(Reverse polarity)
Marco Benocci , PhD – Microcontroller Interfaces – MPHS 2010/2011
- 18 -
Universität Dortmund
I2C
Alma Mater Studiorum
Facoltà di Ingegneria, Bologna
I2C (inter-integrated circuit), Philips1982
Philips Semiconductor I2C specification v2.1
(http://www.nxp.com/acrobat_download2/literature/9398/39340011.pdf)
IC (Inter Communication Bus) fabrication process (NMOS, CMOS, bipolar)
 Half-duplex, synchronous, multi-master bus
 Two wires: serial data (SDA), serial clock (SCL)
 Each device is recognized by a unique address and can operate as either a transmitter or
receiver.
 A master is the device which initiates a data transfer on the bus and generates the clock
signals to permit that transfer.
 At that time, any device addressed is considered a slave.
 Standard-mode, up to 400 kbit/s in the Fast-mode, or up to 3.4 Mbit/s in the High-speed
mode.
 10-bit extended addressing for new designs (7-bit addresses all exhausted).
Focus:
 minimizes interconnections
 eliminates the need for address decoders and other ‘glue logic’
 the multi-master capability allows rapid testing of end-user equipment via external
connections
 simple design/upgrade
DECT cordless phone base-station.
Clones: present restriction of timing and voltage levels, introduction of interrupt signal
• Intel SMBus (System Management Bus): speed 10 a 100 kHz
• Intel PMBus: speed < 400 kHz
Marco Benocci , PhD – Microcontroller Interfaces – MPHS 2010/2011
- 19 -
Universität Dortmund
I2C
Alma Mater Studiorum
Facoltà di Ingegneria, Bologna
Pros
• multimaster
• no chip select or arbitration logic required
• transmission control
• “Clock stretching” – when the slave (receiver) needs more time to process a bit, it can pull SCL low. The master
waits until the slave has released SCL before sending the next bit.
•“General call” broadcast – addresses every device on the bus
Cons
• The number of interfaces connected to the bus is solely dependent on the bus capacitance limit of 400 pF.
• Limited to about 10 feet for moderate speeds.
• Need external hardware: lines pulled high via resistors, pulled down via open-drain drivers (wired-AND)
• Half-duplex
Marco Benocci , PhD – Microcontroller Interfaces – MPHS 2010/2011
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Universität Dortmund
SPI
Alma Mater Studiorum
Facoltà di Ingegneria, Bologna
SPI (Serial Peripheral Interface Bus), found on Motorola's M68HC11 family of CPUs in 2001
• Data is simultaneously transmitted and received.
• Master/slave relationship.
• Interprocessor communications in a multiple-master system.
• 3-pin and 4-pin SPI operation
• 7- or 8-bit data length
• 2 data signals:
• MOSI – master data output, slave data input
• MISO – master data input, slave data output
• 2 control signals:
• SCLK – clock
• /SS – slave select
(no addressing)
• The serial clock line [SCK] synchronizes shifting and sampling of the information on the two serial data lines.
• The master places the information onto the MOSI line a half-cycle before the clock edge that the slave device uses to latch
the data.
•Four possible timing relationships can be chosen by using the Clock Polarity [CPOL] and Clock Phase [CPHA] bits in the
Serial Peripheral Control Register [SPCR].
•Data rates as high as 1 Mbit per second are accommodated when the system is configured as a master; rates as high as 2
Mbits per second are accommodated when the system is operated as a slave.
Marco Benocci , PhD – Microcontroller Interfaces – MPHS 2010/2011
- 21 -
Universität Dortmund
SPI
Alma Mater Studiorum
Facoltà di Ingegneria, Bologna
Pros
 Full duplex communication
 Higher throughput than I²C or SMBus
 Flexibility for the bits transferred (arbitrary choice of message size, content, and purpose)
 Simple hardware interfacing
o Typically lower power requirements than I²C or SMBus due to less circuitry (including pullups)
o Slaves use the master's clock, and don't need precision oscillators
o Slaves don't need a unique address -- unlike I²C or GPIB or SCSI
o Signals are unidirectional allowing for easy Galvanic isolation
Cons
 Requires more pins on IC packages than I²C
 No in-band addressing; out-of-band chip select signals are required on shared buses
 No hardware flow control
 No hardware slave acknowledgment
 Supports only one master device
 Only handles short distances compared to RS-232, RS-485, or CAN-bus
Marco Benocci , PhD – Microcontroller Interfaces – MPHS 2010/2011
- 22 -
Universität Dortmund
SPI vs. I2C
Alma Mater Studiorum
Facoltà di Ingegneria, Bologna
SPI Simultaneus transfert
As the register transmits the byte to the slave on
the MOSI signal line, the slave transfers the
contents of its shift register back to the master on
the MISO signal line, exchanging the contents of
the two shift registers.
For point-to-point, SPI is simple and efficient

Less overhead than I2C due to lack of
addressing, plus SPI is full duplex.
For multiple slaves, each slave needs
separate slave select signal

More effort and more hardware than I2C
SPI
I2C
Marco Benocci , PhD – Microcontroller Interfaces – MPHS 2010/2011
- 23 -
Universität Dortmund
PWM
AlmaMater
MaterStudiorum
Studiorum
Alma
Facoltà
Ingegneria,Bologna
Bologna
Facoltà
di di
Ingegneria,
PWM (Pulse-Width Modulated): communication throw a width-capture of a precise external pulse
i.e. drive servo-motors
Marco Benocci , PhD – Microcontroller Interfaces – MPHS 2010/2011
- 24 -
Universität Dortmund
Interface a digital smart sensor
Alma Mater Studiorum
Facoltà di Ingegneria, Bologna
LIS302DL
o 3-axis digital accelerometer
o Range: - ±2g or ±8g
o Output Interface: I2C or SPI (CMOS)
o Max Data rate (ODR): 400Hz
o Bandwidth: ODR/2
o Turn-on Time: 3/ODR
o Sensitivity: 18 or 72 mg/LSB
No external conditioning circuit need
for C/V convertion and voltage translation
Internal 8 bit ADC
Serial Bridge
Capacitive
Sensor
Advantages provided by Smart sensors
(ctrl flags, interrupts, energy duty-cycling, ...)
Marco Benocci , PhD – Microcontroller Interfaces – MPHS 2010/2011
- 25 -
Universität Dortmund
Interface a digital sensor: SPI
Serial Bridge
Register Memory Mapping
Alma Mater Studiorum
Facoltà di Ingegneria, Bologna
Control Registers
SPI Communication Management
1. Init (RW=0; AD5:0=0x20; D7:0=0x47)  Enable X, Y, Z axis –
DR=400; FS = ±2g | n.b. CTRL_REG 2 does not need deafult value
change
Enable Filter for Free-Fall Wake Up
2. Read X Low Data (RW=1; AD5:0=0x29)  Read D7:0 value
Marco Benocci , PhD – Microcontroller Interfaces – MPHS 2010/2011
- 26 -
Universität Dortmund
Field Busses
Alma Mater Studiorum
Facoltà di Ingegneria, Bologna
Fieldbus (or field bus) is the name of a family of industrial computer network protocols used for
real-time distributed control, now standardized as IEC 61158.
A complex automated industrial system — such as a manufacturing assembly line — usually
needs an organized hierarchy of controller systems to function. In this hierarchy there is usually a
Human Machine Interface (HMI) at the top, where an operator can monitor or operate the system.
This is typically linked to a middle layer of programmable logic controllers (PLC) via a non-timecritical communications system (e.g. Ethernet). At the bottom of the control chain is the fieldbus
which links the PLCs to the components which actually do the work such as sensors, actuators,
electric motors, console lights, switches, valves and contactors (Wiki).
Relevant examples:
• CAN: Controller Area Network
• Profibus: Process Field Bus
• TTP: Time-Triggered-Protocol
• FlexRay: designed to be faster and more reliable than CAN and TTP
• MAP: bus designed for car factories
• IEEE 488: designed for laboratory equipment
• EIB: European Installation Bus
Marco Benocci , PhD – Microcontroller Interfaces – MPHS 2010/2011
- 27 -
Universität Dortmund
Alma Mater Studiorum
Facoltà di Ingegneria, Bologna
Marco Benocci , PhD – Microcontroller Interfaces – MPHS 2010/2011
- 28 -
Universität Dortmund
ORCAD/Cadence
Alma Mater Studiorum
Facoltà di Ingegneria, Bologna
• Computer-Aided Engineering (CAE) tools cover all
aspects of engineering design from drawings to analysis to
manufacturing.
• Computer-aided design (CAD) is a category of CAE that is
related to the physical layout and drawing development of a
system design.
• Electronic design automation (EDA) reduce development
time and cost because they allow designs to be simulated
and analyzed prior to purchasing and manufacturing
hardware.
• Capture contains extensive parts libraries that may be used to generate schematics that
stand alone or that interact with PSpice, or Layout, or both simultaneously.
•The pins on a Capture part can be mapped into the pins of a PSpice model and/or the pins of a
physical package in Layout.
• PSpice is a CAE tool that contains the mathematical models for performing simulations, and
Layout is a CAD tool that converts a symbolic schematic diagram into a physical representation
of the design.
• Netlists are used to interconnect parts within a design and connect each of the parts with its
model and footprint.
• In addition to being a CAD tool, Layout also functions as a front-end CAM tool by generating
the data on which other CAM.
Marco Benocci , PhD – Microcontroller Interfaces – MPHS 2010/2011
- 29 -
Universität Dortmund
PCB
Alma Mater Studiorum
Facoltà di Ingegneria, Bologna
Printed Circuit Board (PCB)
A PCB consists of two basic parts:
 a substrate (the board)
 printed wires (the copper traces).
The substrate provides a structure that physically holds the circuit components and printed wires
in place and provides electrical insulation between conductive parts.
A common type of substrate is FR4, which is a fi berglass–epoxy laminate. Substrates are also
made from Tefl on, ceramics, and special polymers.
During manufacturing the PCB starts out as a copper clad substrate as shown in Fig. 1-2. A
rigid substrate is a C-stage laminate (fully cured epoxy). The copper cladding may be copper
that is plated onto the substrate or copper foil that is glued to the substrate.
A substrate can have copper on one or both sides. Multilayer boards are made up of one or more
single- or double-sided substrates called cores. A core is a copper-plated epoxy laminate. The
cores are glued together with one or more sheets of a partially cured epoxy.
Marco Benocci , PhD – Microcontroller Interfaces – MPHS 2010/2011
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Universität Dortmund
PCB Design Process: OrCAD Layout
Alma Mater Studiorum
Facoltà di Ingegneria, Bologna
Layout is used to design the PCB by generating a digital description of the board layers for
photoplotters and CNC machines, which are used to manufacture the boards.
There are separate layers for :
• routing copper traces on the top, bottom, and all inner layers;
• drill hole sizes and locations;
• soldermasks;
• silk screens;
• solder paste;
• part placement;
• board dimensions.
Marco Benocci , PhD – Microcontroller Interfaces – MPHS 2010/2011
- 31 -
Universität Dortmund
OrCAD Layout: File format
Alma Mater Studiorum
Facoltà di Ingegneria, Bologna
Layout format files (.MAX)
Layout uses .MAX extension while you are designing your board.
Gerber Files
When you are ready to fabricate your board, Layout postprocesses the design and converts it
into a format that the photoplotters and CNC machines can use (Gerber files).
A separate Gerber file is created for each of the layers (distinguible by the extension).
Assembly layers
These files are used for automated assembly of a finished board.
• Solder-paste layer. It is used to make a contact mask for selectively applying solder paste
onto the PCB’s pads so that components can be reflow soldered to the board. There may be a
solder-paste layer for the top side of the board (.SPT) and one for the bottom side (.SPB).
• Assembly layer, which contains information for automatic component placement machines
(pick-and-place machines) as to the part type, its position, and its orientation on the board. As
with the soldermask, there may be an assembly layer for the top side of the board (.AST) and
one for the bottom side (.ASB).
Marco Benocci , PhD – Microcontroller Interfaces – MPHS 2010/2011
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Universität Dortmund
Overview of the Design Flow
Alma Mater Studiorum
Facoltà di Ingegneria, Bologna
Basic procedure for generating a schematic in Capture and converting the schematic to a
board design in Layout:
1. Start Capture and set up a PCB project using the PC Board wizard.
2. Make a circuit schematic using OrCAD Capture.
3. Use Capture to generate a Layout netlist and save it as a .MNL file for Layout.
4. Start Layout and select a PCB technology template (.TCH file).
5. Save the Layout project as a .MAX project file.
6. Use Layout to import the .MNL netlist into the .MAX file.
7. Make a board outline.
8. Position the parts within the board outline.
9. Autoroute the board.
10. Run the postprocessor to generate fi les used to manufacture the PCB.
Marco Benocci , PhD – Microcontroller Interfaces – MPHS 2010/2011
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Universität Dortmund
Industry Standards
Alma Mater Studiorum
Facoltà di Ingegneria, Bologna
How big and what shape should the board outline be?
Where should the parts be placed and in what order?
What kind of layer stackup should be used?
How wide and far apart should the traces be routed?
What grounding and shielding techniques should be used?
Is there a “right” way to do it, and who says so?
There are several standards related to PCB design to solve these questions.
The organizations below set standards that may be guides, rules for certification, or even laws:
• Institute for Printed Circuits (IPC-Association Connecting Electronics Industries)
• Electronic Industries Alliance (EIA)
• Joint Electron Device Engineering Council (JEDEC)
• International Engineering Consortium (IEC)
• Military Standards
• American National Standards Institute (ANSI)
• Institute of Electrical and Electronics Engineers (IEEE)
Marco Benocci , PhD – Microcontroller Interfaces – MPHS 2010/2011
- 34 -
Universität Dortmund
PCB Issues
Alma Mater Studiorum
Facoltà di Ingegneria, Bologna
Performance classes
PCBs can fall into any of three end-use performance classes.
● Class 1, General Electronic Products, includes general consumer products (televisions, electronic
games, and personal computers) that are not expected to have extended service lives and are not likely
to be subjected to extensive test or repairability requirements.
● Class 2, Dedicated-Service Electronic Products, includes commercial and military products that have
specifi c functions such as communications, instrumentation, and sensor systems, from which high
performance is expected over a longer period of time. Since these items usually have a higher cost they
are usually repairable and must meet stricter testing requirements.
● Class 3, High-Reliability Electronic Products, includes commercial and military equipment that has to
be highly reliable under a wide range of environmental conditions. Examples include critical medical
equipment and weapons systems. They typically have more stringent test specifi cations and possess
greater environmental robustness and reworkability.
Producibility levels
The three producibility levels are:
● Level A, general design—preferred complexity
● Level B, moderate design—standard complexity
● Level C, high design—reduced producibility complexity
Marco Benocci , PhD – Microcontroller Interfaces – MPHS 2010/2011
- 35 -
Universität Dortmund
Minimum recommended spacing
Alma Mater Studiorum
Facoltà di Ingegneria, Bologna
Marco Benocci , PhD – Microcontroller Interfaces – MPHS 2010/2011
- 36 -
Universität Dortmund
Ground Issues
Alma Mater Studiorum
Facoltà di Ingegneria, Bologna
Typical signal and return connection schemes.
Left) parallel connected
Right) Series connected
Signal and return connection parallel and series schemes in Layout
Marco Benocci , PhD – Microcontroller Interfaces – MPHS 2010/2011
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Universität Dortmund
Common ground plane
Alma Mater Studiorum
Facoltà di Ingegneria, Bologna
• Solve routing problems
• If the signal path is relatively close to the return path, the return signal will automatically flow
through the GND plane directly below the signal trace (in DC circuits, current follows the path
of least resistance).
• AC currents will follow the path of least impedance and, particularly on PCBs, the path of
least inductance
In a typical PCB the power distribution system contains one or more power and ground planes.
The power and ground planes are like very wide traces (have little inductance) and are usually adjacent
to each other (high capacitance).
Ok for the power distribution system
Problem occurs in high-speed digital systems when gates switch from one state to another: switching
noise.
Marco Benocci , PhD – Microcontroller Interfaces – MPHS 2010/2011
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Universität Dortmund
Switching Noise
Alma Mater Studiorum
Facoltà di Ingegneria, Bologna
the supply voltages across the PCB while the gate is switching
Because the power and ground planes are not superconductors there is a drop in voltage between
the supply pins of the gate and where power is connected to the PCB (same for the return plane).
Remember that there is always some amount of resistance and inductance even on the so-called
ground plane.
Rail collapse: the drop in the positive rail
Ground bounce: the rise in ground potential.
The primary purpose of bypass capacitors in digital circuits is to promote a stable PCB power
distribution system and prevent rail collapse and ground bounce. The bypass capacitors act as
lowpass fi ters and short out power supply transients (noise) before they get to the amplifliers.
Marco Benocci , PhD – Microcontroller Interfaces – MPHS 2010/2011
- 39 -
Universität Dortmund
Split power and ground planes
Alma Mater Studiorum
Facoltà di Ingegneria, Bologna
The solution to the problem of digital noise being injected into analog circuitry through the
supply planes is to segregate the analog components from the digital ones and eliminate
common return paths. Segregating the components is straightforward; the components are
physically placed in different places on the board.
a) Continuous plane
b) Split plane
c) Moated plane
d) Isolated, coutinuous plane
Marco Benocci , PhD – Microcontroller Interfaces – MPHS 2010/2011
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