Produzione del chip standard cell AMchip03
Per SVT a CDF
•
Breve descrizione dei tests del prototipo e risultati
1. il chip funziona (up to now) 
2. ma yield e’ basso 
3. 37% perfetti, ~55-60% perfetti+ “quasi” perfetti
•
Descrizione dell’ upgrade AM++ e sua flessibilita’
•
Descrizione diverse possibilita’ di produzione 
e loro costi  Servono almeno 70 kE aggiuntivi

AMchip03 status
.
• 126 dies produced by IMEC, 116 of which
came packaged. Arrived on September 30th
The SCAM chip
• Simulation test vectors translated for the Test stand.
• Test of all the chips in the Test stand
Output to
Logic
Analyzer
Inputs from
Pattern
Generator
AMChip
socket
Test Vectors
Three types of tests:
• Random Tests: 1) Generate Random Patterns
2) Generate Random Configurations
3) Send random Hits + good hits
Roads to next
AMchip
• Memory Tests
• Feature Tests
1)
2)
3)
4)
FSM
Jtag
Extest I/O
Opcode
Jtag
Pattern
Flux
Pattern
Bank
Roads
From AM
SCAMChip internal Structure
AMchip03 Test: Results
• We passed all the 116 chips through an intensive test at 100 nS.
• 8 AM chips tested @30nS to be mounted on a first LAMB++
Yield (flawless) ≈ 37%
Yield (flawless + defective Patterns < 2) ≈ 53.5%
Yield (flawless + defective Patterns < 5) ≈ 59.5%
Yield Expected 68%, based on IMEC’s predictions.
Yield puo’ fluttuare moltoproduzione calcolata su 35%
BLOCCO 0
Pattern
Layer
Chip
0x0
0x100
0x800
1A3
2
23
BLOCCO 1
Pattern
Layer
819
1
Chip
34
0x900
0x1000
0x1100
BLOCCO 2
Pattern
Layer
106B
4
1000
0
1190
2
BLOCCO 3
Pattern
Layer
Chip
8
76
0x1800
2
0x1900
0x200
240
1
78
0xA00
AFC
?
18
0x1200
122A
12E0
3
2
25
98
0x1A00
0x300
378
4
109
0xB00
B0C
0
1
0x1300
133A
1367
0
2
9
33
0x1B00
0x400
4CA
1
17
0xC00
C39
?
87
0x1400
1421
?
111
0x1C00
0x4FF
4
0xCFF
0x14FF
4
Chip
19C6
1924
5
2
103
6
196C
5-4-1-0
62
0x1CFF
8
3
1 solo pattern wrong (preliminary tests)
1 < Pattern wrong < 5
Pattern wrong>4 o other errors
= 19/116
= 7/116
= 46/116
16.4 %
6.0%
39.7%
Good
= 43/116
37.1%
Test Stand – Vme Crate
A complete system with an AMS/Pulsar, a
merger and an AM++ with FPGAs has been
tested with success @33MHz.
Currently Testing with a Lamb++
equipped with 8 AMchips
Next step: adding a
Lamb++ with 16
“defective”AMchips.
At the moment we can load 5000
patterns in AMchips and send Random
Test Hits + good Hits.
# Lambs (16 Amchips)/
wedge
SVTupg/ tot
SVTnow chips
2 Lamb: 160 kpatt/wedge
8 Lamb: 640 kpatt/wedge
Gain of the 2004
SVT upgrade
SVT Phyiscs
Trigger
rates:
examples
@3x1032
5
20
Current SVT
13 KHz
keuro
384
+ spare ~500
1536
+ spare ~2000
53
2003
93
2004
Upgraded SVT
23 KHz
Maximum L1 rate for 5% L2 dead time @3x1032
Trigger
Z b-b
Hadronic B decay
L1 Trigger rate
26 KHz
177 KHz
Installazione
2005
Eventuale completamento
AM++ (9U VME)
LAMB GLUE
MAX 2005: 640 Kpatt/wedge
AM
VME
INTERFACE
INDI
LAMB
CONNECTORs
PIPELINE
REGISTERs
Input
Control
Clock
Distrib.
HIT/ROAD
CONNECTOR
TOP
GLUE
To
AMS
Year chip
boards
devel. Total
2003? 120 kE
10 kE (test b.)
5 kE
135 kE
2004
-
10 kE (protot.)
30 kE
40 kE
2005
53 kE
+40 kE
100 kE (produc.)
+70 kE (produzione)
+40 kE tests di qualifica
+25 kE package sottile
153 k
+40 kE
Upgrade 2004: 600 chips
Upgrade 2005: 2000 chips buoni
Ipotesi 35/50% yield – fondi 95 + 60 keuros = 155 ke
Due strategie di produzione: MPW e Pilot Run
MPW: buono per piccole produzioni usando maschere
del prototipo
Si paga solo il silicio ed i 5/6 del wafer si buttano!
Con 128 wafers 1700/2430 chips - costo=240 keuro
Pilot Run: nuove maschere 210 k$
1 wf 250 chips contro i 38 MPW
PILOT
RUN
#wafers
12
25
#good
chips
costo
keuro
1050/1500 215
2188/3125 225
Mancanti
keuro
60
70
costo
altrettanti
chip
26.4 k$
55 k$
Conclusioni
•Il chip funziona (up to now)
•Yield ~ 37%
•Forse si possono usare anche i quasi perfetti: 55-59%
•Yield puo’ fluttuare moltoproduzione calcolata su 35%
•Pilot run: migliore garanzia per avere 2000 chips
•Si richiedono 70 keuro aggiuntivi per il pilot run
Backup slides
Upgrade 2004: 600 chips
Upgrade 2005: 2000 chips buoni
Ipotesi 35/50% yield – fondi 95 + 60 keuros = 155 ke
MPW
Wafers
#good
chips
costo
keuro
Mancanti
keuro
costo
/chip
50
75
100
128
665/950
998/1425
1330/1900
1700
130
185
190
240
0
30
35
85
184/128.5 E
177/124 E
138/96 E
138 E
PILOT
RUN
12
25
#good
chips
costo
keuro
1050/1500 215
2188/3125 225
Mancanti
keuro
60
70
costo
/chip
198/139–32/22 E
101/71 –21/15 E
Tsukuba
Chicago
Tempi di processamento: come agisce l’upgrade ?
SVT exec time ~ proporzionale # candidati da fittare
raw data from
SVX front end
NUOVA AM piu’ grande
Hit Finders
Sequencer
Associative Memory
COT tracks
fromXTRP
roads
x 12 phi sectors
Road Warrior
12 fibers
hits
Track Fitter
Merger
hits
to Level 2
Hit Buffer
Ricetta per velocizzare il tempo di esecuzione di SVT:
1.
pattern piu’ sottili (AM grande)  meno fits.
2. Road Warrior per rimuovere i ghosts
TEMPI DI REALIZZAZIONE
• Nuova AM-board: inizio estate 2004 (Pisa)
durante estate 2004: test con FPGA (Pisa)
• Progetto prototipo AM-chip: luglio 2004 (Ferrara-Pisa)
consegna chip ~2 mesi – disponibile ad ottobre.
• Nuova LAMB: montare nuovo AM-chip a ottobre 2004 (Pisa)
• test del chip + scheda: ottobre – dicembre 2004 (Pisa-Ferrara)
• produzione: inizio 2005 (Pisa-Ferrara)
• installazione: estate 2005 (Pisa-Ferrara)
•
Altri DAQ/Trigger upgrade: previsti nel 2006
Road Warrior:
.
.
.
(~60 k$ Fermilab)
messa in opera entro fine 2003  F. Spinella
(in funzione)
RW+TF: F>50ms = 21%
Pulsar (Pulser And Recorder) Design
Custom
Mezzanine
AUX card
Mezzanine slots
Pulsar
Works
up to
100MHz
Top view
Bottom view
I/O Mezzanine cards for:
 S-LINK (CERN/LHC)
 Hotlink
 TAXI
 to be specified
Three ALTERA APEX 20K400 FPGAs
Self-testable
Modular, lego-style open design
 Replacing > 10 CDF board types
 all CDF, many ATLAS connectors/standards
AMchip
L. Zanello
Trigger/DAQ Upgrades for Run IIb
• Need to Maintain or increase
bandwidth
– Luminosity   Rate (=s*L)
– Luminosity  inter/x-ing
 Complexity (and fakes)
 Event Size, Exec. time
– All sphysics to tape
• L1 Bandwidth (output to L2)
– XFT Purity strigger(L1, L2)
– SVT, L2 L2 Exec. t L1
Bandwidth
• L2 Bandwidth (output to L3)
– COT TDC Readout rate
– Level 3 Processing L3 Exec. t
– Event Builder Readout rate
• L3 Bandwidth (output to tape)
– CSL Tape rate (not under IIb
project)