VIPIX, pSuperB, (SuperB)
Atlas/FTK
M. Villa
04/11/2010
VIPIX (2009-2011)
• Sviluppo di sensori a pixel in
integrazione verticale
–
–
–
–
–
–
High bandwidth
High rate (100 MHz/cm2)
Data push
Time identification 100 ns
Spatial resolution 12 um
Low budget material (<<1 Xo)
Optical In
Power In
• Caratterizzazione dei sensori su
fascio
– Trigger/DAQ
– Memorie associative
Opto Electronics
and/or Voltage Regulation
Digital Layer
Analog Layer
Sensor Layer
Physicist’s Dream
50 um
Optical Out
Sensor Technology
MAPS 2D
Readout
architecture
core version
AREO
Hybrid 2D
APSEL3D,
4D
SORTEX
Hybrid 3D
APSEL3D_T
C
FE4D32x128
SQUARE
Mixing
interdetto
MAPS 3D
3DMAPX
3DHPX
Caratteristiche ed innovazioni introdotte nelle varie architetture:
•1 : AREO (Apsel family Read Out)
• Apsel family read out
• MP management logic
• Parallel hit encoding
• Sparsified column readout
• 2 : SORTEX (SORTed EXtraction)
• Time sorted hit extraction
• horizontal parallelization (submatrices)
• zone sparsification / output compression
• I2C-like interface
• 3: SQUARE (Sequenced QUery Advanced REadout)
• No MP
• Matrix TS query for time sequenced readout
• Single column parallel sparsified readout (higher efficiency)
• higher Time Resolution (more robust time sorting for short BC)
Nomi
Indicativi
prossime
sottomissioni
APSEL4D
APSEL3D
Type MAPS
Techn. STM 0.13
Matrix 32x128
Type MAPS
Techn. STM 0.13
Matrix 8x32
APSEL3D _TC
Type 3D MAPS
Techn. Tezz. C. 0.13
Matrix 8x32
FE4D32x128 alias SuperPX0
Architetture
scalate per matrici
di dimensioni
ridote
(Più o meno in scala fra loro)
Type Hybrid
Techn. STM 0.13
Matrix 32x128
4
Chip dimensions for Layer0 pixel module
12-05-2010
1-3 mm 0.5 mm
Beam axis
0.25 mm
10 mm
~ 75 Pad – pitch 130 mm
50 mm pitch
Active area=128mm2
Submatrix 2
Submatrix 1
Piste data line di 2 sottomatrici
0.120 mm cut line
Produrremo un ritaglio!
0.16 mm
14.79-16.79 mm
~ 75 Pad – pitch 130 mm
Submatrix 3
~ 75 Pad – pitch 130 mm
256x192 pixel matrix
Submatrix 4
Readout=10-30mm2
12.8 mm
0.16 mm
Area~3xarea from FE32x128
10.56 mm
Piste data line di 2 sottomatrici
6-07-2010
Chip dimensions for APSELVI 128x96
Chartered/Tezzaron
1.6 mm 0.5 mm
Beam axis
0.25 mm
5 mm
~ 38 Pad – pitch 130 mm
50 mm pitch
Active area=32mm2
Submatrix 2: 128x48
8.99 mm
0.16 mm
~ 38 Pad – pitch 130 mm
128x96 pixel matrix
~ 38 Pad – pitch 130 mm
Submatrix 1: 128x48
Readout=8mm2
6.4 mm
Piste data line di 2 sottomatrici
0.120 mm cut line
0.16 mm
Area~x2x area from FE32x128
5.56 mm
Piste data line di 2 sottomatrici
Parallelamente…. DAQ: EDRO V2
• Born as a SLIM5 DAQ
board
– Recycling several
boards: CMS muon
trigger mezzanine,
VME, CMS barrel
sorter, S-Link & TTCrq
• Used happily in beam tests
• Reused in ATLAS as the
LUCID DAQ board:
– Bunch-by-bunch
luminosity evaluation
• Next use:
– ZDC luminosity
measurements
– VIPIX DAQ
– Vertical Slice “DO”
board
VIPIX DAQ duties
Obbiettivo principale:
Test beam settembre 2011
• Installare in gennaio-giugno tutta
l’infrastruttura di beam test a Bologna:
– 4 piani strip; 4 scintillatori;
– 2 maps digitali (Apsel-like) + 1 analogico
– 1-4 MAPS Perugine (RAPS)
– 1 chip MIMOROMA3
pSuperB: progetto pilota SuperB
(R&D only)
• Coinvolgimento di Bologna sulle tematiche
del vertex detector: 80-90 % overlap con
VIPIX
– Chip di lettura
– DAQ
The SuperB Silicon Vertex Tracker
BaBar SVT
20 cm
old beam pipe
new beam pipe
Layer0
30 cm
40 cm
Bp p decay mode, bg=0.28, beam
Dt resolution (ps)
pipe X/X0=0.42%, hit resolution =10 mm
MAPS (2 layers)
Hybrid Pixels
(single layer)
•
•
•
•
•
5 Layers of double-sided Si strip sensor
Low-mass design. (Pt < 2.7 GeV)
Stand-alone tracking for slow particles.
97% reconstruction efficiency
Resolution ~15μm at normal incidence
•Can use Babar SVT design for R>3cm
•Reduced beam energy asymmetry (7x4 GeV vs.
9x3.1 GeV) requires improved vertex resolution
•Layer0 very close to the IP (R~ 1.5 cm) with
low material budget
•Background levels depends steeply on radius
•Layer0 needs to have fine granularity and
radiation tolerance
• Layer0 subject to large
background and needs to be
extremely thin:
> 5MHz/cm2, > 1MRad/yr, < 1 %X0
R&D on strip/pixel options
•
Layer0 with striplets (technology mature but need some work):
– Readout chip! (totally missing)
– Module assembly with multilayer fanout (still uncovered !)
– HDI/transition card electronics (partly covered by M.Citterio assuming
similar to pixel option…not enough!)
Hybrid pixel:
• Prototype Front-end chip for hybrid pixel (32x128, 50 um pitch) tested
– Results in fair agreement with simulation
•
•
Pixel sensor matrix produced and tested: good quality
FE chip + sensor matrix bump-bonding in june and test in lab in September
CMOS MAPS:
• Pixel readout architecture for next matrix (3D MAPS with 2 CMOS layers
interconnected, ~Dec 2010) could work in data push and triggered mode
– triggered readout reduces pixel module complexity (lower speed for links & less
material for pixel bus)
DAQ reading chain for L0-L5
HDI +Transition card+FEB+ROM
Pi+Bo+Bg/Pv
Frascati, 28/09/10
Milano
DAQ chain independent on
the chosen FE options
Bologna
12
ATLAS/FTK
• Progetto di tracking veloce in ATLAS basato
sulle memorie associative
• Si dovrebbe collocare tra il primo livello di trigger
ed il secondo. E’ denominato L1.5
• “Feature extraction on L1 data”
• Approvato in ATLAS in primavera
• 2 Steps:
Siamo coinvolti
– 2012 Vertical-slice test (parassitaggio su un
quadrante)
Ci vogliono ma non
– 2013… Installazione su tutto ATLAS
abbiamo dato la
disponibilita’ per ora
Event selection –trigger
LHC frequency 40 MHz
Events frequency on tape/disc
100 Hz
Selection is necessary
3 trigger levels
first level (HW)
HLT (SW)
second level
Event Filter
FTK: HW processor to
reconstruct charged
tracks at LVL2
Pt>1 GeV
Inside the whole ID
FTK
Works in parallel with DAQ
Can be added even after the
data taking has began
~off-line quality
Francesco Crescioli
14
Fast Tracker – Struttura interna
Ricieves hits from DAQ
Comunicates with
Associative Memory boards
Sends hits & found roads
to the Fitter
6 boards in parallel
Each DO handles 1-2 layers

Performs pattern
recognition on Super Bins
 Send back found roads to
DO

Struttura modulare
EDRO in
Vertical slice
Piu` processori possono
lavorare in parallelo
E` possibile iniziare con
una versione prototipale e
poi aggiungere
Roads and hits with high
risolution are composed and the
Linear Fitis executed to select
real tracks, stored in a buffer
ready for the LVL2 CPUs
Francesco Crescioli
15
Guadagni con FTK
• Miglior rapporto segnale/fondo; migliore
capacità di discriminazione ai livelli di
trigger bassi maggiore statistica finale
Bs→μμ Results (CDF – ATLAS – ATLAS + FTK)
CDF with 780 pb-1 of data 16/3/2006
BR < 1.0x10-7 @95% CL
ATLAS (2006)
ATLAS + FTK
LVL1 2 muons Pt>6 GeV
LVL1 singolo muone Pt>6 GeV
30 fb-1
30 fb-1
21 B events 60 Backgr.
BR < 6.6x10-9 @90% CL
2nd m Pt>6 GeV
66 events (|η|<1 prototype)
178 events (|η|<2.5|)
background LVL2 Rate for 2nd m
Pt>3 GeV O(10Hz)
Joint venture
• Vertical Slice:
– Pisa: AM board aggiornata
– Americani: Interfaccia vs rivelatori a Pixel
– Frascati: ricezione hit e clustering (EPMC)
– Bologna: Data organizer
(firmware/software)
Mezzanina ricezione hits
• Compatibilita’ EDRO;
• Usabile anche per SuperB
• Progetto finito; produzione 10 pezzi a breve
Riassumendo
• Impegni certi:
–
–
–
–
–
VIPIX: sviluppo architetture RO, layout 2 chips
VIPIX: test beam 2011 – Software/firmware
pSuperB/SuperB: sovrapposizione VIPIX
ATLAS/FTK: commitment fino alla vertical slice (2012)
ATLAS/FTK: sviluppo software e firmware (Ing. Ele.)
• Impegni possibili/da decidere:
– ATLAS/FTK oltre il test del 2012
– SuperB (se approvato) quante forze?
– Oltre il 2011: continuazione di VIPIX?
• Impegni probabili: Prin2009/Vipix+FTK-like
• Impegni chiusi: Prin2007