1
2
3
4
5
6
7
8
ZH9 Block Diagram (AMD Nile Platform)
DDR III,800 MT/s
Geneva
AMD ASB2 CPU
HDT
P4
UNBUFFERED
DDRIII SODIMM
Channel A
P15
K125 (Athlon SC) 12W HT1
K325 (Athlon DC) 12W HT1
A
A
(812 balls ; 27x27mm)
P2~5
HyperTransport LINK
16x16
LVDS MUX
LVDS CON
RS880M
P16
HyperTransport LINK0 CPU I/F
TMDS(PCIE 4x1)
HDMI CON
DDRIII
DX10 IGP
SIDE PORT
DDRIII 128MB
P17
SIDE PORT MEMORY
DAC
VGA CON
P16
B
P6
LVDS
B
1X16 PCIE I/F
PCIE GEN1
1X4 PCIE I/F WITH SB
6X1 PCIE I/F
0
LAN-AR8152L
(21x21mm)
P6~9
P21
2
A-Link X4
4
3G
P23
SB820M
1
2
WLAN/WiMAX
HD AUDIO I/F
USB2.0(14)+1.1(2)
P23
SATA III(6 PORTS)
Headphone Jack
MIC In Jack
Digital MIC
Speaker Header
AZALIA CODEC
CX20672
P19
4X1 PCIE GEN2 I/F
SIM CARD
8
INT. RTC
SATA II I/F
C
Mobile 2.5" HDD
INT. CLK
5
Bluetooth
P19
PCI/PCI BDGE
P23
C
P22
EC
P18
HD AUDIO
LPC I/F
ACPI 1.1
1
3
7
6
0
(23x23mm)
USB 2.0
P10~14
CCD
USB PORT
(Lower Right) P20
P16
USB PORT
(Upper Right) P20
USB PORT
(Left)
P20
P24
+1.8V
SYSTEM
5V/3V PCU
Winbond NPCE781L
P27
AMD CPU Core
CPU_NB Core
P28
DDR 1.5VSUS
P30
+1.1V
(VLDT)
P25
Discharge/+2.5V/
P33
VDDR
SMBUS
Thermal Protection
P31
l.c
om
EC
P32
D
ai
P29
Keyboard
P34
Touch Pad
P18
P18
SPI Flash
Charger
P25
P26
PWM FAN
tm
NB CORE
ho
P26
CPU
THERMAL SENSOR
P4
f@
BATTERY CHAGER
LPC
Quanta Computer Inc.
P4
in
5 IN1
CARDREADER
he
Document Number
xa
PROJECT : ZH9
Size
Rev
4A
Block Diagram
Date:
1
2
3
4
5
6
7
Sunday, March 28, 2010
Sheet
1
8
of
40
D
5
4
3
2
1
D
D
U16A
<6> HT_CADINN[15..0]
<6> HT_CLKINP[1..0]
C
<6> HT_CLKINN[1..0]
<6> HT_CTLINP[1..0]
<6> HT_CTLINN[1..0]
<6> HT_CADOUTP[15..0]
<6> HT_CADOUTN[15..0]
<6> HT_CLKOUTP[1..0]
<6> HT_CLKOUTN[1..0]
<6> HT_CTLOUTP[1..0]
<6> HT_CTLOUTN[1..0]
HT_CADINP[15..0]
HT_CADINN[15..0]
HT_CLKINP[1..0]
HT_CLKINN[1..0]
HT_CTLINP[1..0]
HT_CTLINN[1..0]
HT_CADOUTP[15..0]
HT_CADOUTN[15..0]
HT_CLKOUTP[1..0]
HT_CLKOUTN[1..0]
HT_CTLOUTP[1..0]
HT_CTLOUTN[1..0]
B
AB6HT_CADOUTP15
AB5HT_CADOUTN15
AB9HT_CADOUTP14
AB8HT_CADOUTN14
AC7HT_CADOUTP13
AC6HT_CADOUTN13
AE6HT_CADOUTP12
AE5HT_CADOUTN12
AE9HT_CADOUTP11
AE8HT_CADOUTN11
AH3HT_CADOUTP10
AH4HT_CADOUTN10
AK3HT_CADOUTP9
AK4HT_CADOUTN9
AH1HT_CADOUTP8
AH2HT_CADOUTN8
Y1 HT_CADOUTP7
Y2 HT_CADOUTN7
Y4 HT_CADOUTP6
Y3 HT_CADOUTN6
AB1HT_CADOUTP5
AB2HT_CADOUTN5
AB4HT_CADOUTP4
AB3HT_CADOUTN4
AD4HT_CADOUTP3
AD3HT_CADOUTN3
AF1HT_CADOUTP2
AF2HT_CADOUTN2
AF4HT_CADOUTP1
AF3HT_CADOUTN1
AK1HT_CADOUTP0
AK2HT_CADOUTN0
W7
W6
U6
U5
R7
R6
P6
P5
L6
L5
J6
J5
H4
H3
G6
G5
T3
T4
T2
T1
P3
P4
P2
P1
M2
M1
K3
K4
K2
K1
H2
H1
L0_CADIN_H15
L0_CADIN_L15
L0_CADIN_H14
L0_CADIN_L14
L0_CADIN_H13
L0_CADIN_L13
L0_CADIN_H12
L0_CADIN_L12
L0_CADIN_H11
L0_CADIN_L11
L0_CADIN_H10
L0_CADIN_L10
L0_CADIN_H9
L0_CADIN_L9
L0_CADIN_H8
L0_CADIN_L8
L0_CADIN_H7
L0_CADIN_L7
L0_CADIN_H6
L0_CADIN_L6
L0_CADIN_H5
L0_CADIN_L5
L0_CADIN_H4
L0_CADIN_L4
L0_CADIN_H3
L0_CADIN_L3
L0_CADIN_H2
L0_CADIN_L2
L0_CADIN_H1
L0_CADIN_L1
L0_CADIN_H0
L0_CADIN_L0
HT_CLKINP1
HT_CLKINN1
M8
M7
L0_CLKIN_H1
L0_CLKIN_L1
L0_CLKOUT_H1
L0_CLKOUT_L1
AF6HT_CLKOUTP1
AF5HT_CLKOUTN1
HT_CLKINP0
HT_CLKINN0
M3
M4
L0_CLKIN_H0
L0_CLKIN_L0
L0_CLKOUT_H0
L0_CLKOUT_L0
AD1HT_CLKOUTP0
AD2HT_CLKOUTN0
HT_CTLINP1
HT_CTLINN1
Y6
Y5
L0_CTLIN_H1
L0_CTLIN_L1
L0_CTLOUT_H1
L0_CTLOUT_L1
Y8 HT_CTLOUTP1
Y9 HT_CTLOUTN1
HT_CTLINP0
HT_CTLINN0
V2
V1
L0_CTLIN_H0
L0_CTLIN_L0
L0_CTLOUT_H0
L0_CTLOUT_L0
V4 HT_CTLOUTP0
V3 HT_CTLOUTN0
HT LINK
<6> HT_CADINP[15..0]
HT_CADINP15
HT_CADINN15
HT_CADINP14
HT_CADINN14
HT_CADINP13
HT_CADINN13
HT_CADINP12
HT_CADINN12
HT_CADINP11
HT_CADINN11
HT_CADINP10
HT_CADINN10
HT_CADINP9
HT_CADINN9
HT_CADINP8
HT_CADINN8
HT_CADINP7
HT_CADINN7
HT_CADINP6
HT_CADINN6
HT_CADINP5
HT_CADINN5
HT_CADINP4
HT_CADINN4
HT_CADINP3
HT_CADINN3
HT_CADINP2
HT_CADINN2
HT_CADINP1
HT_CADINN1
HT_CADINP0
HT_CADINN0
L0_CADOUT_H15
L0_CADOUT_L15
L0_CADOUT_H14
L0_CADOUT_L14
L0_CADOUT_H13
L0_CADOUT_L13
L0_CADOUT_H12
L0_CADOUT_L12
L0_CADOUT_H11
L0_CADOUT_L11
L0_CADOUT_H10
L0_CADOUT_L10
L0_CADOUT_H9
L0_CADOUT_L9
L0_CADOUT_H8
L0_CADOUT_L8
L0_CADOUT_H7
L0_CADOUT_L7
L0_CADOUT_H6
L0_CADOUT_L6
L0_CADOUT_H5
L0_CADOUT_L5
L0_CADOUT_H4
L0_CADOUT_L4
L0_CADOUT_H3
L0_CADOUT_L3
L0_CADOUT_H2
L0_CADOUT_L2
L0_CADOUT_H1
L0_CADOUT_L1
L0_CADOUT_H0
L0_CADOUT_L0
C
B
A
A
Quanta Computer Inc.
PROJECT : ZH9
Size
Document Number
Rev
4A
ASB2 HT I/F 1/4
Date:
5
4
3
Sunday, March 28, 2010
2
Sheet
2
of
1
40
A
B
C
D
E
Processor Memory Interface
R29
AC29
AE28
<15> M_A_BANK2
<15> M_A_BANK1
<15> M_A_BANK0
3
<15>
<15>
<15>
<15>
<15>
<15>
<15>
<15>
<15>
<15>
<15>
<15>
<15>
<15>
<15>
<15>
<15>
<15>
<15>
<15>
M_A_DQSP7
M_A_DQSN7
M_A_DQSP6
M_A_DQSN6
M_A_DQSP5
M_A_DQSN5
M_A_DQSP4
M_A_DQSN4
M_A_DQSP3
M_A_DQSN3
M_A_DQSP2
M_A_DQSN2
M_A_DQSP1
M_A_DQSN1
M_A_DQSP0
M_A_DQSN0
M_A_CLKP1
M_A_CLKN1
M_A_CLKP2
M_A_CLKN2
2
MA_ADD15
MA_ADD14
MA_ADD13
MA_ADD12
MA_ADD11
MA_ADD10
MA_ADD9
MA_ADD8
MA_ADD7
MA_ADD6
MA_ADD5
MA_ADD4
MA_ADD3
MA_ADD2
MA_ADD1
MA_ADD0
MA_BANK2
MA_BANK1
MA_BANK0
K30
J29
G29
F29
L28
L29
H29
H27
MA_CHECK7
MA_CHECK6
MA_CHECK5
MA_CHECK4
MA_CHECK3
MA_CHECK2
MA_CHECK1
MA_CHECK0
J27
J26
AJ11
AK12
AG15
AH15
AH22
AG22
AG26
AH26
E28
F28
E25
F25
G17
H17
E12
F12
MA_DQS_H8
MA_DQS_L8
MA_DQS_H7
MA_DQS_L7
MA_DQS_H6
MA_DQS_L6
MA_DQS_H5
MA_DQS_L5
MA_DQS_H4
MA_DQS_L4
MA_DQS_H3
MA_DQS_L3
MA_DQS_H2
MA_DQS_L2
MA_DQS_H1
MA_DQS_L1
MA_DQS_H0
MA_DQS_L0
AK18
AJ17
AH17
AG17
Y28
Y27
AB27
AB26
W27
W26
P26
M26
D18
F19
E20
E19
MA_CLK_H7
MA_CLK_L7
MA_CLK_H6
MA_CLK_L6
MA_CLK_H5
MA_CLK_L5
MA_CLK_H4
MA_CLK_L4
MA_CLK_H3
MA_CLK_L3
MA_CLK_H2
MA_CLK_L2
MA_CLK_H1
MA_CLK_L1
MA_CLK_H0
MA_CLK_L0
<15>
<15>
M_A_CKE1
M_A_CKE0
M30
M28
<15>
<15>
M_A_ODT1
M_A_ODT0
AJ29
AF27
AJ30
AG29
MA1_ODT1
MA1_ODT0
MA0_ODT1
MA0_ODT0
<15>
<15>
M_A_CS#1
M_A_CS#0
AH29
AE29
AH30
AF29
AC27
AF30
AE27
<15> M_A_RAS#
<15> M_A_CAS#
<15> M_A_WE#
<15> M_A_RST#
<15> MEMHOT_MA#
R285
L27
*0/J_4M32
MA_DATA63
MA_DATA62
MA_DATA61
MA_DATA60
MA_DATA59
MA_DATA58
MA_DATA57
MA_DATA56
MA_DATA55
MA_DATA54
MA_DATA53
MA_DATA52
MA_DATA51
MA_DATA50
MA_DATA49
MA_DATA48
MA_DATA47
MA_DATA46
MA_DATA45
MA_DATA44
MA_DATA43
MA_DATA42
MA_DATA41
MA_DATA40
MA_DATA39
MA_DATA38
MA_DATA37
MA_DATA36
MA_DATA35
MA_DATA34
MA_DATA33
MA_DATA32
MA_DATA31
MA_DATA30
MA_DATA29
MA_DATA28
MA_DATA27
MA_DATA26
MA_DATA25
MA_DATA24
MA_DATA23
MA_DATA22
MA_DATA21
MA_DATA20
MA_DATA19
MA_DATA18
MA_DATA17
MA_DATA16
MA_DATA15
MA_DATA14
MA_DATA13
MA_DATA12
MA_DATA11
MA_DATA10
MA_DATA9
MA_DATA8
MA_DATA7
MA_DATA6
MA_DATA5
MA_DATA4
MA_DATA3
MA_DATA2
MA_DATA1
MA_DATA0
MA_DM8
MA_DM7
MA_DM6
MA_DM5
MA_DM4
MA_DM3
MA_DM2
MA_DM1
MA_DM0
MA_CKE1
MA_CKE0
M_A_DQ[0..63]
M_A_DQ63
AG11
M_A_DQ62
AH11
M_A_DQ61
AJ12
M_A_DQ60
AJ14
M_A_DQ59
AF11
M_A_DQ58
AF12
M_A_DQ57
AG12
M_A_DQ56
AH12
M_A_DQ55
AK14
M_A_DQ54
AF15
M_A_DQ53
AH19
M_A_DQ52
AK20
M_A_DQ51
AF14
M_A_DQ50
AG14
M_A_DQ49
AF17
M_A_DQ48
AG19
M_A_DQ47
AG20
M_A_DQ46
AJ20
M_A_DQ45
AF22
M_A_DQ44
AK24
M_A_DQ43
AF19
M_A_DQ42
AF20
M_A_DQ41
AJ23
M_A_DQ40
AG23
M_A_DQ39
AF23
M_A_DQ38
AF25
M_A_DQ37
AH27
M_A_DQ36
AK30
M_A_DQ35
AJ25
M_A_DQ34
AG25
M_A_DQ33
AJ26
M_A_DQ32
AJ28
D28M_A_DQ31
G28M_A_DQ30
D26M_A_DQ29
E26M_A_DQ28
F30M_A_DQ27
E29M_A_DQ26
F27M_A_DQ25
H26M_A_DQ24
H25M_A_DQ23
D24M_A_DQ22
H22M_A_DQ21
E22M_A_DQ20
F26M_A_DQ19
G26M_A_DQ18
D22M_A_DQ17
G23M_A_DQ16
G22M_A_DQ15
G20M_A_DQ14
G15M_A_DQ13
F15M_A_DQ12
D20M_A_DQ11
F22M_A_DQ10
D16M_A_DQ9
E17M_A_DQ8
H15M_A_DQ7
H14M_A_DQ6
G12M_A_DQ5
H12M_A_DQ4
E15M_A_DQ3
E14M_A_DQ2
E11M_A_DQ1
F11M_A_DQ0
H30
AL12M_A_DM7
AK16M_A_DM6
AK22M_A_DM5
AJ27M_A_DM4
E27 M_A_DM3
E23 M_A_DM2
H19 M_A_DM1
G14 M_A_DM0
<15>
M_A_DM[0..7] <15>
P33
P31
AJ33
T32
T31
AD32
T33
V32
U33
V33
V31
W33
Y31
Y33
Y32
AC33
MB_ADD15
MB_ADD14
MB_ADD13
MB_ADD12
MB_ADD11
MB_ADD10
MB_ADD9
MB_ADD8
MB_ADD7
MB_ADD6
MB_ADD5
MB_ADD4
MB_ADD3
MB_ADD2
MB_ADD1
MB_ADD0
R33
AD33
AE33
MB_BANK2
MB_BANK1
MB_BANK0
K33
K31
G32
F32
L33
K32
H31
G33
MB_CHECK7
MB_CHECK6
MB_CHECK5
MB_CHECK4
MB_CHECK3
MB_CHECK2
MB_CHECK1
MB_CHECK0
J33
H32
AM14
AN14
AL20
AM20
AN26
AM26
AN30
AM30
D33
D32
B28
A28
A21
B20
B16
A15
MB_DQS_H8
MB_DQS_L8
MB_DQS_H7
MB_DQS_L7
MB_DQS_H6
MB_DQS_L6
MB_DQS_H5
MB_DQS_L5
MB_DQS_H4
MB_DQS_L4
MB_DQS_H3
MB_DQS_L3
MB_DQS_H2
MB_DQS_L2
MB_DQS_H1
MB_DQS_L1
MB_DQS_H0
MB_DQS_L0
AN22
AM22
AN21
AM21
AA32
AA33
AB33
AB32
AB31
AB30
AD31
AD30
C22
B22
A22
A23
MB_CLK_H7
MB_CLK_L7
MB_CLK_H6
MB_CLK_L6
MB_CLK_H5
MB_CLK_L5
MB_CLK_H4
MB_CLK_L4
MB_CLK_H3
MB_CLK_L3
MB_CLK_H2
MB_CLK_L2
MB_CLK_H1
MB_CLK_L1
MB_CLK_H0
MB_CLK_L0
N33
P32
MB_CKE1
MB_CKE0
AK31
AH31
AK32
AH33
MB1_ODT1
MB1_ODT0
MB0_ODT1
MB0_ODT0
MA1_CS_L1
MA1_CS_L0
MA0_CS_L1
MA0_CS_L0
AK33
AF33
AJ32
AF31
MB1_CS_L1
MB1_CS_L0
MB0_CS_L1
MB0_CS_L0
MA_RAS_L
MA_CAS_L
MA_WE_L
AF32
AH32
AG33
MB_RAS_L
MB_CAS_L
MB_WE_L
L32
M33
MA_RESET_L
FREE|MA_EVENT_L
MB_DATA63
MB_DATA62
MB_DATA61
MB_DATA60
MB_DATA59
MB_DATA58
MB_DATA57
MB_DATA56
MB_DATA55
MB_DATA54
MB_DATA53
MB_DATA52
MB_DATA51
MB_DATA50
MB_DATA49
MB_DATA48
MB_DATA47
MB_DATA46
MB_DATA45
MB_DATA44
MB_DATA43
MB_DATA42
MB_DATA41
MB_DATA40
MB_DATA39
MB_DATA38
MB_DATA37
MB_DATA36
MB_DATA35
MB_DATA34
MB_DATA33
MB_DATA32
MB_DATA31
MB_DATA30
MB_DATA29
MB_DATA28
MB_DATA27
MB_DATA26
MB_DATA25
MB_DATA24
MB_DATA23
MB_DATA22
MB_DATA21
MB_DATA20
MB_DATA19
MB_DATA18
MB_DATA17
MB_DATA16
MB_DATA15
MB_DATA14
MB_DATA13
MB_DATA12
MB_DATA11
MB_DATA10
MB_DATA9
MB_DATA8
MB_DATA7
MB_DATA6
MB_DATA5
MB_DATA4
MB_DATA3
MB_DATA2
MB_DATA1
MB_DATA0
AN13
AL14
AL16
AN17
AN12
AM12
AM16
AN16
AL18
AN19
AM24
AN24
AM18
AN18
AL22
AN23
AM25
AL26
AN28
AL28
AL24
AN25
AN27
AM28
AM29
AL30
AL32
AL33
AK28
AN29
AM31
AM32
E33
D31
B31
A31
F33
F31
C32
B32
C30
A29
B26
A26
B30
A30
A27
C26
A24
B24
C18
A18
A25
C24
C20
A19
C16
A16
B14
A13
B18
A17
C14
A14
MB_DM8
MB_DM7
MB_DM6
MB_DM5
MB_DM4
MB_DM3
MB_DM2
MB_DM1
MB_DM0
H33
AN15
AN20
AK26
AN31
C33
C28
A20
D14
4
3
2
MB_RESET_L
FREE|MB_EVENT_L
l.c
om
4
U16C
DDR III: CHANNEL A
M_A_A15 P30
M_A_A14 M29
M_A_A13AG28
M_A_A12 P28
M_A_A11 T30
M_A_A10AC28
M_A_A9 P27
M_A_A8 R26
M_A_A7 R27
M_A_A6 U28
M_A_A5 V30
M_A_A4 U27
M_A_A3 Y30
M_A_A2 AB29
M_A_A1 W29
M_A_A0 AC26
DDR III: CHANNEL B
U16B
<15> M_A_A[0..15]
ho
tm
BOM@ASB2_CPU
f@
Quanta Computer Inc.
PROJECT : ZH9
in
<Layout note>
Route as 60 ohms with
5/10 W/S from CPU pins.
Note>
: AJ00105VT00
: AJ0K125VT02
: AJ0K325VT02
: AJ0K625VT03
Size
Document Number
xa
<BOM
V105
K125
K325
K625
BOM@ASB2_CPU
ai
1
Rev
4A
Date:
A
B
C
D
Sunday, March 28, 2010
he
ASB2 DDRIII MEMORY 2/4
Sheet
E
3
of
40
1
5
4
CPU Thermal monitor(THM)
3
2
1
<Layout note>
Keep net PWRGD, LDT_STOP#, LDT_RST# no stub
+3V
<20100303(C3A)>
Reserve R266,C315,C316,U15,R276,R410 and stuff R51~R53,R48,Q7~Q9,D2,D3,R411, for AMD SB-TSI.
L37
3A/30ohm_6
CPU_LDT_RST#
CPU_PWRGD
CPU_LDT_STOP#
W/S= 15 mil/20mil
+CPUVDDA
+2.5V
R309
R319
R308
300/J_4
300/J_4
300/J_4
+1.5V
DCR:0.03ohm
R266
*200/J_4
C372
180P/50V_4
C361
4.7U/6.3V_6
C351
0.22U/6.3V_4
C345
3300P/50V_4
+3V_THMVCC
<20091029(A1A)_47337_ASB2_scl_nda_1.00>
CPU_PRESENT_L net are pulled up to VDDIO with 1Kohm
CPU_TEST20_SCANCLK2 and CPU_TEST21_SCANEN net are pulled down to GND with 1Kohm
<25> 2ND_MBCLK
<25> 2ND_MBDATA
D
U15
+3V
8
7
6
R275
4
2
*10K/J_4
SCLK
VCC
SDA
DXP
ALERT#
DXN
OVERT#
GND
C315
250mA
*0.1U/10V_4
CLK_CPU_BCLKP
<10> CLK_CPU_BCLKP
H_THERMDA
1
C367
3900P/25V_4
CPU CLK Keep trace from resisor to CPU within 0.6"
R314
169/F_4
keep trace from caps to CPU within 1.2"
2
C316
3
*2200P/50V_4
CLK_CPU_BCLKN
<10> CLK_CPU_BCLKN
*G786P81U
3
<12> THERM_ALERT#
THERM_ALERT#_R
1
*2N7002K
Q17
+3V
R276
CLK_CPU_BCLKP_C
CLK_CPU_BCLKN_C
ADDRESS: 0x4C(98H)
(1001100)
<20091202(A1A)_Confirm with AMD's Reden>
RSVD_SA0 is a VSS pin, so connect to GND.
CPU_TDI
CPU_TRST#
CPU_TCK
CPU_TMS
CPU_DBREQ#
+1.5VSUS
<28> CPU_VDD_FB_L
+1.5VSUS
2
3
R42
1K/J_4
R52
1K/J_4
Q8
MMBT3904
1
SVC
SVD
T63
C1
B2
CPU_SVC_R
CPU_SVD_R
39.2/F_4
SIC
SID
RSVD_SA0
ALERT_L
AM8
AL8
AK8
AN8
THERMDC
THERMDA
THERMTRIP_L
PROCHOT_L
AL6
AM5
AK6
AN6
H_THERMDC
H_THERMDA
CPU_THERMTRIP_L#
CPU_PROCHOT_L#
TDI
TRST_L
TCK
TMS
G9
R311
1K/F_4
3
1
CPU_TEST25_H_BYPASSCLK_H
CPU_TEST25_L_BYPASSCLK_L
CPU_TEST19_PLLTEST0
CPU_TEST18_PLLTEST1
C344
C355
0.01U/25V_4 1000P/50V_4
CPU_SID
2
D2
RB501V-40
THERM_ALERT#
3
T78
T79
Q9
MMBT3904
1
AM6 RSVD3
RSVD3
AJ9
CPU_PRESENT_L
M_VREF
M_ZN_H
M_ZN_L
A9
B9
A5
B6
R270
R127
R126
R55
R267
R128
R123
R124
R47
R274
R54
R125
*300/J_4
*300/J_4
*300/J_4
1K/J_4
1K/J_4
510/F_4
1K/J_4
1K/J_4
1K/J_4
1K/J_4
1K/J_4
*0/short_4
D
<20091202(A1A)_Confirm with AMD's Reden>
CPU_TEST23_TSTUPD PD with 1K and add a test point
R330
*300/J_4
+1.1V_CPU_VLDT
T58
CPU_PRESENT_L
V10 CPU_HTREF1
CPU_HTREF0
V9
HTREF1
HTREF0
CPU_TEST9_ANALOGIN
G8
CPU_TEST17_BP3
CPU_TEST16_BP2
CPU_TEST15_BP1
CPU_TEST14_BP0
F8
C8
D9
E8
BYPASSCLK_H
BYPASSCLK_L
PLLTEST0
PLLTEST1
Place them to CPU within 1.5"
R76
R75
44.2/F_4
44.2/F_4
+1.1V_CPU_VLDT
C
T82
T8
T6
T59
CPU_TEST7_ANALOG_T
CPU_TEST6_DIECRACKMON
CPU_TEST3
CPU_TEST2
BP3
BP2
BP1
BP0
C6
AH7
AK5
AJ7
B10 CPU_TEST29_H_FBCLKOUT_P
A10 CPU_TEST29_L_FBCLKOUT_N R310
FBCLKOUT_H
FBCLKOUT_L
SCANCLK1
TSTUPD
SCANSHIFTEN
SCANEN
SCANCLK2
ANALOGIN
CPU_ALERT_L
ANALOG_T
DIECRACKMON
GATE0
DRAIN0
PLLCHRZ_H
PLLCHRZ_L
SINGLECHAIN
BURNIN_L
ANALOGOUT
DIG_T
+3V
CPU FAN(THM)
CPU_TEST15_BP1
CPU_TEST14_BP0
CPU_TEST21_SCANEN
CPU_TEST20_SCANCLK2
CPU_TEST25_L_BYPASSCLK_L
CPU_TEST19_PLLTEST0
CPU_TEST18_PLLTEST1
CPU_TEST24_SCANCLK1
CPU_TEST22_SCANSHIFTEN
CPU_TEST23_TSTUPD
CPU_TEST9_ANALOGIN
+1.5VSUS
Route as 80ohm, diff
2
Q7
MMBT3904
1
1K/J_4
300/J_4
510/F_4
1K/J_4
1K/J_4
CPU_DBRDY
H9
DBRDY
VSS_SENSE
VLDT_SENSE
VDD_SENSE
VDDNB_SENSE
VDDIO_SENSE
VDDR_SENSE
CPU_M_VREF A11
M_ZP
AM9
M_ZN
AN9
R268
R307
R135
R264
R269
CPU_TEST10_ANALOGOUT
DBREQ_L
D2
E2
E1
D1
D3
C2
CPU_PRESENT_L
CPU_DBREQ#
CPU_TEST25_H_BYPASSCLK_H
CPU_TEST26_BURNIN_L
CPU_TEST27_SINGLECHAIN
AN7 CPU_TDO
TDO
CPU_SIC
RB501V-40
2ND_MBDATA
M31 CPU_CORE_TYPE
RSVD|CORE_TYPE
PWROK
LDTSTOP_L
RESET_L
CLOSE TO CPU WITHIN 1"
2
1
D3
CPU_VLDT_FB_H
CPU_M_VREF
R271
2
2ND_MBCLK
T60
<28> CPU_VDD_FB_H
<28> CPU_VDDNB_FB_H
<30> CPU_VDDIO_FB_H
<33> CPU_VDDR_FB_H
R324
1K/F_4
R53
2.2K/J_4
R50
1K/J_4
CLKIN_H
CLKIN_L
CPU_SIC
AN4
CPU_SID
AN5
RSVD_SA0
AM2
CPU_ALERT_L AN3
<check list>
Layout Note:Routing 10:10 mils and away
from noise source with ground gard
+1.5VSUS
C
MISC
SideBand Temp sense I2C
*10K/J_4
R48
2.2K/J_4
A6
A7
CPU_PWRGD
D10
CPU_LDT_STOP# E9
CPU_LDT_RST#
F9
THERM_OVERT#
R51
2.2K/J_4
U16D
VDDA_1
VDDA_2
3900P/25V_4
<10> CPU_PWRGD
<8,10> CPU_LDT_STOP#
<10> CPU_LDT_RST#
H_THERMDC
5
C366
W/S= 15 mil/20mil
+CPUVDDA A8
+CPUVDDA B8
AK7
AG8
AK9
AH9
AM7
CPU_TEST24_SCANCLK1
CPU_TEST23_TSTUPD
CPU_TEST22_SCANSHIFTEN
CPU_TEST21_SCANEN
CPU_TEST20_SCANCLK2
G11
H11
AJ8
AM4
D7
B5
CPU_TEST28_H_PLLCHRZ_P
CPU_TEST28_L_PLLCHRZ_N
CPU_TEST27_SINGLECHAIN
CPU_TEST26_BURNIN_L
CPU_TEST10_ANALOGOUT
CPU_TEST8_DIG_T
80.6/F_4
T7
route as differential as short as possible.
testpoint under package
T15
T14
T81
AG9
M_TEST
+1.5VSUS
R44
10K/J_4
<25>
<Visual Comment>
R39
10K/J_4
FANSIG
+5V
*0/J_4 THERM_FAN#
THERM_ALERT#
*0/short_4
2
THERM_OVERT# R410
CN13
R34
B
<25>
1
CPUFAN#
FAN_PWM_CN
3
Q6
1
CPU_THERMTRIP_L#
1
25
36
4
10K/J_4
2
R411
R45
1K/J_4
B
3
MMBT3904
R41
*0/J_4
R46
*0/short_4
CPU_THERMTRIP#
SYS_SHDN#
<11>
<27,34>
FAN CONN
Q5
MMBT3904
R31
+5V
*0/short_6
FAN CONN
Follow PDC pin define
+5V_FANVCC
R265
+1.5VSUS
300/J_4
CPU_PROCHOT_L#
C29
R273
*0/short_4
R272
*0/short_4
CPU_PROCHOT#
<10>
SB_PROCHOT# <12>
0.01U/25V_4
HDT Connector
+1.5VSUS
CPU_DBREQ#
CPU_DBRDY
CPU_TCK
CPU_TMS
CPU_TDI
CPU_TRST#
CPU_TDO
*[email protected]/10V_4
KEY
2
4
6
8
10
12
14
16
18
20
22
24
25
Q18
3
2
R371
*[email protected]/J_4
1
3
5
7
9
11
13
15
17
19
21
23
A
C431
Serial VID
+1.5V
+3V
CPU_LDT_RST#
1
To override VID,
Remove three 0ohms and install 220ohm of CPU_PWRGD to GND
+1.5V
R321
*2.2K/J_4
+1.5VSUS
+1.5V
R326
R331
1K/J_4
*1K/J_4
+1.5VSUS
+1.5V
R322
R328
1K/J_4
*1K/J_4
<20091028(A1A)_47337_ASB2_scl_nda_1.00>
SVC/SVD net are pulled up to VDDIO with 1Kohm
*HDT@FDV301N
CPU_SVC_R
CPU_SVD_R
CPU_PWRGD
R312
R318
R323
*0/short_4
*0/short_4
*0/short_4
CPU_LDT_RST_HT#
R313
R317
R329
CPU_SVC
CPU_SVD
CPU_PWRGD_SVID_REG
CPU_SVC <28>
CPU_SVD <28>
CPU_PWRGD_SVID_REG
Pre-PWROK Metal MODE
SVC
SVD
Voltage Output
0
0
1
1
0
1
0
1
1.1V
1.0V
0.9V
0.8V
VFIX MODE(Don't Support)
Voltage Output
1.4V
1.2V
1.0V
0.8V
Quanta Computer Inc.
<28>
*220/J_4
*220/J_4
*220/J_4
PROJECT : ZH9
Size
CN18
*HDT@HDT CONN
Document Number
Rev
4A
ASB2 CTRL & DEBUG 3/4
Date:
5
A
4
3
2
Sunday, March 28, 2010
Sheet
1
4
of
40
4
3
CPU_CORE
+1.5VSUS
U16F
POWER1
VDD_85
VDD_84
VDD_83
VDD_82
VDD_81
VDD_80
VDD_79
VDD_78
VDD_77
VDD_76
VDD_75
VDD_74
VDD_73
VDD_72
VDD_71
VDD_70
VDD_69
VDD_68
VDD_67
VDD_66
VDD_65
VDD_64
VDD_63
VDD_62
VDD_61
VDD_60
VDD_59
VDD_58
VDD_57
VDD_56
VDD_55
VDD_54
VDD_53
VDD_52
VDD_51
VDD_50
VDD_49
VDD_48
VDD_47
VDD_46
VDD_45
VDD_44
AE12
AD9
AE21
AD21
AD18
AD14
AD12
AD11
AC5
AE18
AC24
AC12
AC10
AB13
AB11
AE14
AA24
AA12
AA10
Y19
Y16
Y14
W5
W20
W18
W15
AE23
V24
V19
V16
V14
T20
T18
T15
T10
R5
R19
R16
R14
AC4
P24
P20
M27
Y26
U26
N32
U32
N30
P29
R28
R30
R32
U29
U30
W28
W30
W32
Y29
AA30
AB28
AE32
AC30
AC32
AE26
AE30
AF28
AG30
AG32
AD25
AA25
AC25
V25
P25
N25
M25
K25
L25
T25
Y25
AB25
VDDIO_1
VDDIO_2
VDDIO_3
VDDIO_4
VDDIO_5
VDDIO_6
VDDIO_7
VDDIO_8
VDDIO_9
VDDIO_10
VDDIO_11
VDDIO_12
VDDIO_13
VDDIO_14
VDDIO_15
VDDIO_16
VDDIO_17
VDDIO_18
VDDIO_19
VDDIO_20
VDDIO_21
VDDIO_22
VDDIO_23
VDDIO_24
VDDIO_25
VDDIO_26
VDDIO_27
VDDIO_28
VDDIO_29
VDDIO_30
VDDIO_31
VDDIO_32
VDDIO_33
VDDIO_34
VDDIO_35
VDDIO_36
VDDIO_37
VDDIO_38
VLDT_A_1
VLDT_A_2
VLDT_A_3
VLDT_A_4
F1
F2
F3
F4
VLDT_B_1
VLDT_B_2
VLDT_B_3
VLDT_B_4
AL1
AL2
AL3
AL4
AK10
AL10
AM10
AN10
VDDR_5
VDDR_6
VDDR_7
VDDR_8
CPU_VDDR
0.8~1.1V
CPU_VDDNB_CORE
A3
A4
B3
B4
C3
C4
VDDNB_1
VDDNB_2
VDDNB_3
VDDNB_4
VDDNB_5
VDDNB_6
B11
PROGEN_L
G7
B7
AH8
AJ6
B25
AM3
AN11
P9
P8
FREE_1
FREE_2
FREE_3
FREE_4
FREE_5
FREE_6
FREE_7
FREE_8
FREE_9
C
BOM@ASB2_CPU
BOM@ASB2_CPU
CPU_CORE
BOTTOM SIDE DECOUPLING
CPU_CORE
15A
<20091028(A1A)_47337_ASB2_scl_nda_1.00>
Add two 4.7uF for CPU_CORE
+ PC43
330U/2V_7343
C85
22U/6.3V_8
C87
22U/6.3V_8
C124
22U/6.3V_8
C123
22U/6.3V_8
C120
0.22U/6.3V_4
C125
0.01U/25V_4
CPU_CORE
U16H
U16G
B1
N2
N22
N23
B13
B15
B17
M21
B19
B21
B23
B27
B29
B33
C10
P10
P14
P16
P19
P7
C31
D11
D13
D15
R1
D17
D19
D21
D23
D25
D27
R15
R18
R2
R20
D29
D30
D8
E30
E32
F14
F17
R8
T14
T16
F20
T19
T24
T9
U1
F23
N1
G1
G19
G2
G25
G27
N10
A12
B12
C12
D12
VDDR_1
VDDR_2
VDDR_3
VDDR_4
POWER2
D
VDD_1
VDD_2
VDD_3
VDD_4
VDD_5
VDD_6
VDD_7
VDD_8
VDD_9
VDD_10
VDD_11
VDD_12
VDD_13
VDD_14
VDD_15
VDD_16
VDD_17
VDD_18
VDD_19
VDD_20
VDD_21
VDD_22
VDD_23
VDD_24
VDD_25
VDD_26
VDD_27
VDD_28
VDD_29
VDD_30
VDD_31
VDD_32
VDD_33
VDD_34
VDD_35
VDD_36
VDD_37
VDD_38
VDD_39
VDD_40
VDD_41
VDD_42
VDD_43
PROCESSOR POWER AND GROUND
+1.1V_CPU_VLDT
U16E
D4
D5
D6
E5
E6
E7
F5
F6
F7
H7
H8
J8
E4
J10
J12
J14
J18
J20
J21
J23
J9
K10
K12
K14
K18
K20
K21
K23
N4
L11
L13
L7
L9
M10
M12
R4
M5
N11
N24
W4
N9
P15
P18
1
C130
180P/50V_4
C106
4.7U/6.3V_6
C105
4.7U/6.3V_6
VSS_1
VSS_28
VSS_29
VSS_30
VSS_2
VSS_3
VSS_4
VSS_27
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_12
VSS_13
VSS_14
VSS_15
VSS_36
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_37
VSS_38
VSS_39
VSS_40
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSS_53
VSS_54
VSS_55
VSS_56
VSS_57
VSS_58
VSS_59
VSS_60
VSS_61
VSS_62
VSS_63
VSS_64
VSS_65
VSS_66
VSS_67
VSS_115
VSS_45
VSS_44
VSS_43
VSS_42
VSS_26
VSS_25
VSS_41
VSS_24
VSS_23
VSS_22
VSS_68
VSS_69
VSS_70
VSS_71
VSS_72
VSS_73
VSS_74
VSS_75
VSS_76
VSS_77
VSS_78
VSS_79
VSS_80
VSS_81
VSS_82
VSS_83
VSS_84
VSS_85
VSS_86
VSS_87
VSS_88
VSS_89
VSS_90
VSS_91
VSS_92
VSS_93
VSS_94
VSS_95
VSS_96
VSS_97
VSS_98
VSS_99
VSS_100
VSS_101
VSS_102
VSS_103
VSS_104
VSS_105
VSS_106
VSS_107
VSS_108
VSS_109
VSS_110
VSS_111
VSS_112
VSS_113
VSS_114
W19
W1
V20
V18
M11
L8
V15
L4
L30
L26
L24
L23
L22
L21
L2
L12
L10
L1
K9
M6
K24
K22
K16
M22
K13
M24
K11
M23
J7
W16
J4
W14
J32
J30
M13
J28
U8
J25
U4
J24
U7
U2
J2
J16
J13
J11
J1
H6
H5
H28
H23
H20
J22
M9
G4
G30
N12
AM19
AF7
AF26
AE7
AF8
AF9
AG1
AG2
AG27
AG4
AG5
AG6
AG7
AE4
AE25
AE24
AE22
AE20
AE2
AE16
AE13
AH14
AE11
AE10
AE1
AD24
AD23
AD22
AH20
AH23
AH25
AH28
AD20
AD16
AD13
AD10
AC9
AC8
A2
AC23
AH5
AJ1
AJ15
W2
A32
W8
Y10
Y15
Y18
AJ19
AJ2
AJ22
AJ4
Y20
Y24
AK11
AK13
Y7
AA1
AA11
CPU_VDDNB_CORE
VSS_207
VSS_167
VSS_166
VSS_165
VSS_168
VSS_169
VSS_170
VSS_171
VSS_172
VSS_173
VSS_174
VSS_175
VSS_176
VSS_164
VSS_163
VSS_162
VSS_161
VSS_160
VSS_159
VSS_158
VSS_157
VSS_177
VSS_156
VSS_155
VSS_154
VSS_153
VSS_152
VSS_151
VSS_178
VSS_179
VSS_180
VSS_181
VSS_150
VSS_149
VSS_148
VSS_147
VSS_146
VSS_145
VSS_214
VSS_144
VSS_182
VSS_183
VSS_184
VSS_116
VSS_213
VSS_117
VSS_118
VSS_119
VSS_120
VSS_185
VSS_186
VSS_187
VSS_188
VSS_121
VSS_122
VSS_189
VSS_190
VSS_123
VSS_124
VSS_125
GND2
CPU_CORE
2
GND1
5
0.7~1.1V
AK15
AK17
AK19
AK21
AA2
AA22
AA23
AK23
AA4
AA9
AB10
AB12
AB21
AB22
AB23
AB24
AK25
AK27
AK29
AJ5
AH6
AL31
AM1
AM13
AB7
AC1
AM15
AM17
AC11
AC13
AC2
AC21
AC22
AM23
AM27
AM33
AN2
AN32
AM11
VSS_191
VSS_192
VSS_193
VSS_194
VSS_126
VSS_127
VSS_128
VSS_195
VSS_129
VSS_130
VSS_131
VSS_132
VSS_133
VSS_134
VSS_135
VSS_136
VSS_196
VSS_197
VSS_198
VSS_199
VSS_200
VSS_201
VSS_202
VSS_203
VSS_137
VSS_138
VSS_205
VSS_206
VSS_139
VSS_140
VSS_141
VSS_142
VSS_143
VSS_208
VSS_209
VSS_210
VSS_211
VSS_212
VSS_215
D
C
BOM@ASB2_CPU
2A
BOM@ASB2_CPU
C86
22U/6.3V_8
C84
22U/6.3V_8
C122
22U/6.3V_8
C121
22U/6.3V_8
C109
0.22U/6.3V_4
C110
0.01U/25V_4
C83
180P/50V_4
C354
22U/6.3V_8
C380
22U/6.3V_8
C371
22U/6.3V_8
PLACE CLOSE TO PROCESSOR AS POSSIBLE
+1.5VSUS
3A
B
CPU_VDDR
1A
C103
22U/6.3V_8
C96
22U/6.3V_8
C129
C79
C325
C322
C75
C114
C108
C76
10U/6.3V_8 10U/6.3V_8 0.22U/6.3V_4 0.22U/6.3V_4 0.22U/6.3V_4 0.22U/6.3V_4 0.22U/6.3V_4 0.22U/6.3V_4
+1.5VSUS<20091028(A1A)_47337_ASB2_scl_nda_1.00>
Add two 0.1uF for +1.5VSUS
C71
4.7U/6.3V_6
C327
0.1U/10V_4
C318
0.01U/25V_4
C72
C73
0.22U/6.3V_4 0.22U/6.3V_4
C77
180P/50V_4
R351
C89
C112
10U/6.3V_8 10U/6.3V_8
C360
4.7U/6.3V_6
C350
C343
0.22U/6.3V_4 0.22U/6.3V_4
1.5A
For VLDT_A
For VLDT_B
*0/short_8 +1.1V_CPU_VLDT
C319
4.7U/6.3V_6
C317
C321
22U/6.3V_8 0.22U/6.3V_4
C320
180P/50V_4
C368
4.7U/6.3V_6
C356
0.22U/6.3V_4
C352
180P/50V_4
l.c
om
DECOUPLING BETWEEN PROCESSOR AND DIMMs
PLACE CLOSE TO PROCESSOR AS POSSIBLE
A
C97
4.7U/6.3V_6
C88
4.7U/6.3V_6
C78
4.7U/6.3V_6
C326
C329
0.22U/6.3V_4 0.22U/6.3V_4
C323
180P/50V_4
tm
ho
C92
4.7U/6.3V_6
Quanta Computer Inc.
C324
180P/50V_4
in
PROJECT : ZH9
f@
+1.5VSUS
ai
<20091028(A1A)_47337_ASB2_scl_nda_1.00>
If VSS plane is cut for VDDIO, place two
0.22uF & 180pF across the VDDIO-VSS
Size
xa
A
Group2
<20091202(A1A)_Follow Bimini Rev1.2>
Add two 10uF for +1.5VSUS
+1.1V
C328
0.1U/10V_4
Group1
Document Number
Rev
4A
ASB2 PWR & GND 4/4
Date:
5
4
3
2
Sunday, March 28, 2010
he
B
Sheet
1
5
of
40
5
4
3
2
1
U20A
D
R320
Y25
Y24
V22
V23
V25
V24
U24
U25
T25
T24
P22
P23
P25
P24
N24
N25
HT_RXCAD0P
HT_RXCAD0N
HT_RXCAD1P
HT_RXCAD1N
HT_RXCAD2P
HT_RXCAD2N
HT_RXCAD3P
HT_RXCAD3N
HT_RXCAD4P
HT_RXCAD4N
HT_RXCAD5P
HT_RXCAD5N
HT_RXCAD6P
HT_RXCAD6N
HT_RXCAD7P
HT_RXCAD7N
PART 1 OF 6
HT_CADOUTP8
HT_CADOUTN8
HT_CADOUTP9
HT_CADOUTN9
HT_CADOUTP10
HT_CADOUTN10
HT_CADOUTP11
HT_CADOUTN11
HT_CADOUTP12
HT_CADOUTN12
HT_CADOUTP13
HT_CADOUTN13
HT_CADOUTP14
HT_CADOUTN14
HT_CADOUTP15
HT_CADOUTN15
AC24
AC25
AB25
AB24
AA24
AA25
Y22
Y23
W21
W20
V21
V20
U20
U21
U19
U18
HT_RXCAD8P
HT_RXCAD8N
HT_RXCAD9P
HT_RXCAD9N
HT_RXCAD10P
HT_RXCAD10N
HT_RXCAD11P
HT_RXCAD11N
HT_RXCAD12P
HT_RXCAD12N
HT_RXCAD13P
HT_RXCAD13N
HT_RXCAD14P
HT_RXCAD14N
HT_RXCAD15P
HT_RXCAD15N
HT_CLKOUTP0
HT_CLKOUTN0
HT_CLKOUTP1
HT_CLKOUTN1
T22
T23
AB23
AA22
HT_RXCLK0P
HT_RXCLK0N
HT_RXCLK1P
HT_RXCLK1N
HT_CTLOUTP0
HT_CTLOUTN0
HT_CTLOUTP1
HT_CTLOUTN1
M22
M23
R21
R20
HT_RXCALP
HT_RXCALN
301/F_4
C23
A24
HT_RXCTL0P
HT_RXCTL0N
HT_RXCTL1P
HT_RXCTL1N
HYPER TRANSPORT CPU I/F
HT_CADOUTP0
HT_CADOUTN0
HT_CADOUTP1
HT_CADOUTN1
HT_CADOUTP2
HT_CADOUTN2
HT_CADOUTP3
HT_CADOUTN3
HT_CADOUTP4
HT_CADOUTN4
HT_CADOUTP5
HT_CADOUTN5
HT_CADOUTP6
HT_CADOUTN6
HT_CADOUTP7
HT_CADOUTN7
D24
D25
E24
E25
F24
F25
F23
F22
H23
H22
J25
J24
K24
K25
K23
K22
HT_CADINP0
HT_CADINN0
HT_CADINP1
HT_CADINN1
HT_CADINP2
HT_CADINN2
HT_CADINP3
HT_CADINN3
HT_CADINP4
HT_CADINN4
HT_CADINP5
HT_CADINN5
HT_CADINP6
HT_CADINN6
HT_CADINP7
HT_CADINN7
HT_TXCAD8P
HT_TXCAD8N
HT_TXCAD9P
HT_TXCAD9N
HT_TXCAD10P
HT_TXCAD10N
HT_TXCAD11P
HT_TXCAD11N
HT_TXCAD12P
HT_TXCAD12N
HT_TXCAD13P
HT_TXCAD13N
HT_TXCAD14P
HT_TXCAD14N
HT_TXCAD15P
HT_TXCAD15N
F21
G21
G20
H21
J20
J21
J18
K17
L19
J19
M19
L18
M21
P21
P18
M18
HT_CADINP8
HT_CADINN8
HT_CADINP9
HT_CADINN9
HT_CADINP10
HT_CADINN10
HT_CADINP11
HT_CADINN11
HT_CADINP12
HT_CADINN12
HT_CADINP13
HT_CADINN13
HT_CADINP14
HT_CADINN14
HT_CADINP15
HT_CADINN15
HT_TXCLK0P
HT_TXCLK0N
HT_TXCLK1P
HT_TXCLK1N
H24
H25
L21
L20
HT_CLKINP0
HT_CLKINN0
HT_CLKINP1
HT_CLKINN1
M24
M25
P19
R18
HT_CTLINP0
HT_CTLINN0
HT_CTLINP1
HT_CTLINN1
B24
B25
HT_TXCALP R115
HT_TXCALN
HT_TXCAD0P
HT_TXCAD0N
HT_TXCAD1P
HT_TXCAD1N
HT_TXCAD2P
HT_TXCAD2N
HT_TXCAD3P
HT_TXCAD3N
HT_TXCAD4P
HT_TXCAD4N
HT_TXCAD5P
HT_TXCAD5N
HT_TXCAD6P
HT_TXCAD6N
HT_TXCAD7P
HT_TXCAD7N
HT_TXCTL0P
HT_TXCTL0N
HT_TXCTL1P
HT_TXCTL1N
HT_RXCALP
HT_RXCALN
HT_TXCALP
HT_TXCALN
HT_CADOUTP[15..0]
HT_CADOUTP[15..0]
HT_CADOUTN[15..0]
<2>
HT_CADOUTN[15..0]
HT_CLKOUTP[1..0]
HT_CLKOUTP[1..0]
HT_CLKOUTN[1..0]
<2>
<2>
HT_CLKOUTN[1..0]
HT_CTLOUTP[1..0]
<2>
HT_CTLOUTP[1..0] <2>
HT_CTLOUTN[1..0]
HT_CTLOUTN[1..0]
HT_CADINP[15..0]
HT_CADINP[15..0]
HT_CADINN[15..0]
<2>
<2>
HT_CADINN[15..0]
<2>
D
HT_CLKINP[1..0]
HT_CLKINP[1..0]
HT_CLKINN[1..0]
<2>
HT_CLKINN[1..0]
HT_CTLINP[1..0]
HT_CTLINP[1..0]
HT_CTLINN[1..0]
<2>
<2>
HT_CTLINN[1..0]
<2>
301/F_4
RS880M
25mils 0.5A
+1.5V_SPM_VDDQ
C
+1.5V
R378
C442
C424
[email protected]/10V_4 [email protected]/10V_4
C425
SPM@1U/10V_4
C
*0/short_6
C441
C436
C439
SPM@1U/10V_4 SPM@10U/6.3V_8 SPM@10U/6.3V_8
U20D
B
SPM_VREFCA
SPM_VREFDQ
M8
H1
SPM_A0
SPM_A1
SPM_A2
SPM_A3
SPM_A4
SPM_A5
SPM_A6
SPM_A7
SPM_A8
SPM_A9
SPM_A10
SPM_A11
SPM_A12
SPM_A13
N3
P7
P3
N2
P8
P2
R8
R2
T8
R3
L7
R7
N7
T3
T7
M7
SPM_BA0
SPM_BA1
SPM_BA2
M2
N8
M3
SPM_CLKP
SPM_CLKN
SPM_CKE
J7
K7
K9
VREFCA
VREFDQ
A0
A1
A2
A3
A4
A5
A6
A7
A8
A9
A10/AP
A11
A12/BC
A13
A14
A15
BA0
BA1
BA2
CK
CK
CKE
DQL0
DQL1
DQL2
DQL3
DQL4
DQL5
DQL6
DQL7
DQU0
DQU1
DQU2
DQU3
DQU4
DQU5
DQU6
DQU7
VDD#B2
VDD#D9
VDD#G7
VDD#K2
VDD#K8
VDD#N1
VDD#N9
VDD#R1
VDD#R9
E3
F7
F2
F8
H3
H8
G2
H7
SPM_DQ2
SPM_DQ1
SPM_DQ3
SPM_DQ0
SPM_DQ7
SPM_DQ4
SPM_DQ5
SPM_DQ6
D7
C3
C8
C2
A7
A2
B8
A3
SPM_DQ11
SPM_DQ8
SPM_DQ12
SPM_DQ14
SPM_DQ9
SPM_DQ10
SPM_DQ15
SPM_DQ13
B2
D9
G7
K2
K8
N1
N9
R1
R9
T52
PAR 4 OF 6
SPM_A0
SPM_A1
SPM_A2
SPM_A3
SPM_A4
SPM_A5
SPM_A6
SPM_A7
SPM_A8
SPM_A9
SPM_A10
SPM_A11
SPM_A12
SPM_A13
AB12
AE16
V11
AE15
AA12
AB16
AB14
AD14
AD13
AD15
AC16
AE13
AC14
Y14
SPM_BA0
SPM_BA1
SPM_BA2
AD16
AE17
AD17
SPM_RAS#
SPM_CAS#
SPM_WE#
SPM_CS#
SPM_CKE
SPM_ODT
+1.5V_SPM_VDDQ
W12
Y12
AD18
AB13
AB18
V14
*SPM@100/F_4
V15
W14
R161
SPM_CLKP
SPM_CLKN
R358
R359
+1.5V_SPM_VDDQ
[email protected]/F_4
[email protected]/F_4
SPM_COMPP AE12
SPM_COMPN AD12
MEM_A0(NC)
MEM_A1(NC)
MEM_A2(NC)
MEM_A3(NC)
MEM_A4(NC)
MEM_A5(NC)
MEM_A6(NC)
MEM_A7(NC)
MEM_A8(NC)
MEM_A9(NC)
MEM_A10(NC)
MEM_A11(NC)
MEM_A12(NC)
MEM_A13(NC)
MEM_BA0(NC)
MEM_BA1(NC)
MEM_BA2(NC)
SBD_MEM/DVO_I/F
U7
MEM_RASb(NC)
MEM_CASb(NC)
MEM_WEb(NC)
MEM_CSb(NC)
MEM_CKE(NC)
MEM_ODT(NC)
MEM_DQ0/DVO_VSYNC(NC)
MEM_DQ1/DVO_HSYNC(NC)
MEM_DQ2/DVO_DE(NC)
MEM_DQ3/DVO_D0(NC)
MEM_DQ4(NC)
MEM_DQ5/DVO_D1(NC)
MEM_DQ6/DVO_D2(NC)
MEM_DQ7/DVO_D4(NC)
MEM_DQ8/DVO_D3(NC)
MEM_DQ9/DVO_D5(NC)
MEM_DQ10/DVO_D6(NC)
MEM_DQ11/DVO_D7(NC)
MEM_DQ12(NC)
MEM_DQ13/DVO_D9(NC)
MEM_DQ14/DVO_D10(NC)
MEM_DQ15/DVO_D11(NC)
AA18
AA20
AA19
Y19
V17
AA17
AA15
Y15
AC20
AD19
AE22
AC18
AB20
AD22
AC22
AD21
SPM_DQ0
SPM_DQ1
SPM_DQ2
SPM_DQ3
SPM_DQ4
SPM_DQ5
SPM_DQ6
SPM_DQ7
SPM_DQ8
SPM_DQ9
SPM_DQ10
SPM_DQ11
SPM_DQ12
SPM_DQ13
SPM_DQ14
SPM_DQ15
MEM_DQS0P/DVO_IDCKP(NC)
MEM_DQS0N/DVO_IDCKN(NC)
MEM_DQS1P(NC)
MEM_DQS1N(NC)
Y17
W18
AD20
AE21
SPM_DQS0P
SPM_DQS0N
SPM_DQS1P
SPM_DQS1N
MEM_DM0(NC)
MEM_DM1/DVO_D8(NC)
W17
AE19
SPM_DM0
SPM_DM1
AE23
AE24
+1.8V_NB_IOPLLVDD18
+1.1V_NB_IOPLLVDD
IOPLLVDD18(NC)
IOPLLVDD(NC)
MEM_CKP(NC)
MEM_CKN(NC)
MEM_COMPP(NC)
MEM_COMPN(NC)
IOPLLVSS(NC)
AD23
MEM_VREF(NC)
AE18
B
L46
L45
[email protected]/220ohm_6
[email protected]/220ohm_6
+1.8V
+1.1V
15mA
26mA
SPM_VREF
C410
C409
[email protected]/6.3V_6 [email protected]/6.3V_6
RS880M
SPM_ODT
SPM_CS#
SPM_RAS#
SPM_CAS#
SPM_WE#
K1
L2
J3
K3
L3
SPM_DQS0P
SPM_DQS1P
F3
C7
SPM_DM0
SPM_DM1
E7
D3
ODT
CS
RAS
CAS
WE
DQSL
DQSU
VDDQ#A1
VDDQ#A8
VDDQ#C1
VDDQ#C9
VDDQ#D2
VDDQ#E9
VDDQ#F1
VDDQ#H2
VDDQ#H9
A1
A8
C1
C9
D2
E9
F1
H2
H9
+1.5V_SPM_VDDQ
+1.5V_SPM_VDDQ
+1.5V_SPM_VDDQ
SPM_DQS0N
SPM_DQS1N
+1.5V_SPM_VDDQ
G3
B7
R376
DML
DMU
DQSL
DQSU
SPM@10K/J_4
T2
<11> SP_DDR3_RST#
L8
RESET
ZQ
R373
A
SPM@243/F_4
J1
L1
J9
L9
NC#J1
NC#L1
NC#J9
NC#L9
VSS#A9
VSS#B3
VSS#E1
VSS#G8
VSS#J2
VSS#J8
VSS#M1
VSS#M9
VSS#P1
VSS#P9
VSS#T1
VSS#T9
VSSQ#B1
VSSQ#B9
VSSQ#D1
VSSQ#D8
VSSQ#E2
VSSQ#E8
VSSQ#F9
VSSQ#G1
VSSQ#G9
A9
B3
E1
G8
J2
J8
M1
M9
P1
P9
T1
T9
B1
B9
D1
D8
E2
E8
F9
G1
G9
SDRAM DDR3
BOM@DDR3 SDRAM
<20091202(A1A)_Confirm with Acer Jimmy>
side port memory use DD3
C443
[email protected]/10V_4
R379
SPM@1K/F_4
C418
[email protected]/10V_4
SPM_VREFDQ
C440
[email protected]/10V_4
R366
SPM@1K/F_4
C414
[email protected]/10V_4
SPM_VREFCA
R377
SPM@1K/F_4
C417
[email protected]/10V_4
R365
SPM@1K/F_4
<BOM NOTE>
w/ sideport: L45,L46:CX8PG221003
w/o sideport: L45,L46:CS00003J951(0ohm)
R357
SPM@1K/F_4
SPM_VREF
C413
[email protected]/10V_4
R356
SPM@1K/F_4
A
<BOM Note>
w/ sideport: U7:
AKD5LGGT506 : SAMSUNG DDRIII 800 1Gb K4W1G1646E-HC12 LF
AKD5LZGTW04 : HYNIX DDRIII 800 1Gb H5TQ1G63BFR-12C LF
AKD5LGGT700 : ATI DDRIII 800 1Gb 23EY2387MA12-SZ LF+HF
w/o sideport: U7 Non-stuff
Quanta Computer Inc.
PROJECT : ZH9
Size
Document Number
RS880-HT LINK/SPMEM I/F 1/4
Date:
5
4
3
2
Sunday, March 28, 2010
Sheet
1
6
of
40
Rev
4A
5
4
3
2
1
U20B
C
<21>
<21>
<23>
<23>
<23>
<23>
PCIE_RXP0
PCIE_RXN0
PCIE_RXP1
PCIE_RXN1
PCIE_RXP2
PCIE_RXN2
PCIE_RXP0
PCIE_RXN0
PCIE_RXP1
PCIE_RXN1
PCIE_RXP2
PCIE_RXN2
B
<10>
<10>
<10>
<10>
<10>
<10>
<10>
<10>
A_RXP0
A_RXN0
A_RXP1
A_RXN1
A_RXP2
A_RXN2
A_RXP3
A_RXN3
D4
C4
A3
B3
C2
C1
E5
F5
G5
G6
H5
H6
J6
J5
J7
J8
L5
L6
M8
L8
P7
M7
P5
M5
R8
P8
R6
R5
P4
P3
T4
T3
GFX_RX0P
GFX_RX0N
GFX_RX1P
GFX_RX1N
GFX_RX2P
GFX_RX2N
GFX_RX3P
GFX_RX3N
GFX_RX4P
GFX_RX4N
GFX_RX5P
GFX_RX5N
GFX_RX6P
GFX_RX6N
GFX_RX7P
GFX_RX7N
GFX_RX8P
GFX_RX8N
GFX_RX9P
GFX_RX9N
GFX_RX10P
GFX_RX10N
GFX_RX11P
GFX_RX11N
GFX_RX12P
GFX_RX12N
GFX_RX13P
GFX_RX13N
GFX_RX14P
GFX_RX14N
GFX_RX15P
GFX_RX15N
AE3
AD4
AE2
AD3
AD1
AD2
V5
W6
U5
U6
U8
U7
GPP_RX0P
GPP_RX0N
GPP_RX1P
GPP_RX1N
GPP_RX2P
GPP_RX2N
GPP_RX3P
GPP_RX3N
GPP_RX4P
GPP_RX4N
GPP_RX5P
GPP_RX5N
AA8
Y8
AA7
Y7
AA5
AA6
W5
Y5
SB_RX0P
SB_RX0N
SB_RX1P
SB_RX1N
SB_RX2P
SB_RX2N
SB_RX3P
SB_RX3N
GFX_TX0P
GFX_TX0N
GFX_TX1P
GFX_TX1N
GFX_TX2P
GFX_TX2N
GFX_TX3P
GFX_TX3N
GFX_TX4P
GFX_TX4N
GFX_TX5P
GFX_TX5N
GFX_TX6P
GFX_TX6N
GFX_TX7P
GFX_TX7N
GFX_TX8P
GFX_TX8N
GFX_TX9P
GFX_TX9N
GFX_TX10P
GFX_TX10N
GFX_TX11P
GFX_TX11N
GFX_TX12P
GFX_TX12N
GFX_TX13P
GFX_TX13N
GFX_TX14P
GFX_TX14N
GFX_TX15P
GFX_TX15N
A5
B5
A4
B4
C3
B2
D1
D2
E2
E1
F4
F3
F1
F2
H4
H3
H1
H2
J2
J1
K4
K3
K1
K2
M4
M3
M1
M2
N2
N1
P1
P2
TX2_HDMI+_C
TX2_HDMI-_C
TX1_HDMI+_C
TX1_HDMI-_C
TX0_HDMI+_C
TX0_HDMI-_C
TXC_HDMI+_C
TXC_HDMI-_C
GPP_TX0P
GPP_TX0N
GPP_TX1P
GPP_TX1N
GPP_TX2P
GPP_TX2N
GPP_TX3P
GPP_TX3N
GPP_TX4P
GPP_TX4N
GPP_TX5P
GPP_TX5N
AC1
AC2
AB4
AB3
AA2
AA1
Y1
Y2
Y4
Y3
V1
V2
PCIE_TXP0_C
PCIE_TXN0_C
PCIE_TXP1_C
PCIE_TXN1_C
PCIE_TXP2_C
PCIE_TXN2_C
SB_TX0P
SB_TX0N
SB_TX1P
SB_TX1N
SB_TX2P
SB_TX2N
SB_TX3P
SB_TX3N
AD7
AE7
AE6
AD6
AB6
AC6
AD5
AE5
A_TXP0_C
A_TXN0_C
A_TXP1_C
A_TXN1_C
A_TXP2_C
A_TXN2_C
A_TXP3_C
A_TXN3_C
PCE_CALRP(PCE_BCALRP)
PCE_CALRN(PCE_BCALRN)
AC8
AB8
NB_PCIECALRP
NB_PCIECALRN
PART 2 OF 6
PCIE I/F GFX
D
PCIE I/F GPP
PCIE I/F SB
C393
C392
C396
C395
C398
C397
C406
C403
[email protected]/10V_4
[email protected]/10V_4
[email protected]/10V_4
[email protected]/10V_4
[email protected]/10V_4
[email protected]/10V_4
[email protected]/10V_4
[email protected]/10V_4
TX2_HDMI+
TX2_HDMITX1_HDMI+
TX1_HDMITX0_HDMI+
TX0_HDMITXC_HDMI+
TXC_HDMI-
<17>
<17>
<17>
<17>
<17>
<17>
<17>
<17>
D
TO HDMI
C
C427
C423
C218
C216
C419
C421
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
[email protected]/10V_4
[email protected]/10V_4
C420
C422
C430
C426
C435
C432
C433
C437
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
PCIE_TXP0
PCIE_TXN0
PCIE_TXP1
PCIE_TXN1
PCIE_TXP2
PCIE_TXN2
<21>
<21>
<23>
<23>
<23>
<23>
TO LAN
TO MINI PCIE 1
TO MINI PCIE 2
B
R168
R162
1.27K/F_4
2K/F_4
A_TXP0
A_TXN0
A_TXP1
A_TXN1
A_TXP2
A_TXN2
A_TXP3
A_TXN3
<10>
<10>
<10>
<10>
<10>
<10>
<10>
<10>
+1.1V
RS880M
RS880 Display Port Support (muxed on GFX)
GFX_TX0,TX1,TX2 and TX3
l.c
om
DP0
AUX0 and HPD0
A
ai
A
GFX_TX4,TX5,TX6 and TX7
tm
Quanta Computer Inc.
DP1
ho
AUX1 and HPD1
f@
PROJECT : ZH9
Document Number
Rev
4A
in
Size
Date:
5
4
3
2
Sunday, March 28, 2010
he
xa
RS880-PCIE I/F 2/4
Sheet
7
1
of
40
5
4
U20C
15mils
+1.8V_NB_AVDDQ
1.4A/220ohm_6
- 74LVC07
<20090810(A1A)_46659_RS880_Errata_nda_1.10>
The R channel's term. R change 140ohm (For the
voltage level mismatch, the Red is higher)
R352
C160
R122
R131
1K/J_4
CRT_R
<16>
CRT_G
+1.8V
NB_ALLOW_LDTSTOP
*0/short_4
<16>
1U/6.3V_4
R129
150/F_4
R120
150/F_4
Graphics PLL power
Graphics PLL power
+1.1V
+1.8V
C388
L40
R121
1.4A/220ohm_6
1.4A/220ohm_6
L10
1.4A/220ohm_6
C159
2.2U/6.3V_6
PCIe PLL power
L15
SCL:20mA
DAC_RSET
SCL:20mA
15mils
15mils
+1.8V_NB_VDDA18HTPLL
SCL:120mA+1.8V_NB_VDDA18PCIEPLL 15mils
1.4A/220ohm_6
C174
R346
*0/short_4
<10> CLK_NB_HTREFP
<10> CLK_NB_HTREFN
<10> NB_REFCLK_P
<10> NB_REFCLK_N
R363
R364
B
CRT_VSYNC
R143
R147
3K/J_4
NB Core
+3V
PLLVDD(NC)
PLLVDD18(NC)
PLLVSS(NC)
H17
VDDA18HTPLL
D8
A10
C10
C12
SYSRESETb
POW ERGOOD
LDTSTOPb
ALLOW _LDTSTOP
CLK_NB_HTREFP
CLK_NB_HTREFN
C25
C24
HT_REFCLKP
HT_REFCLKN I
E11
F11
REFCLK_P/OSCIN(OSCIN)
REFCLK_N(PW M_GPIO3)
GFX_REFCLKP
GFX_REFCLKN
I/O
U1
U2
GPP_REFCLKP
GPP_REFCLKN
I/O
CLK_SBLINKP
CLK_SBLINKN
V4
V3
GPPSB_REFCLKP(SB_REFCLKP)
GPPSB_REFCLKN(SB_REFCLKN)
LCD_DATA
LCD_CLK
A9
B9
B8
A8
B7
A7
I2C_DATA
I2C_CLK
DDC_DATA/AUX0N(NC)
DDC_CLK/AUX0P(NC)
AUX1P(NC)
AUX1N(NC)
B10
STRP_DATA
R347
*150/F_4
2K/J_4
AUX_CAL
G11
RSVD
C8
B18
A18
A17
B17
D20
D21
D18
D19
TXCLK_LP(DBG_GPIO1)
TXCLK_LN(DBG_GPIO3)
TXCLK_UP(PCIE_RESET_GPIO4)
TXCLK_UN(PCIE_RESET_GPIO1)
B16
A16
D16
D17
CRT_HSYNC
TXLCLKOUT+ <16>
TXLCLKOUT- <16>
LVDS or DVI/ HDMI PLL power
C386
2.2U/6.3V_6
VDDLTP18(NC)
VSSLTP18(NC)
A13
B13
+1.8V_NB_VDDLTP18
VDDLT18_1(NC)
VDDLT18_2(NC)
VDDLT33_1(NC)
VDDLT33_2(NC)
A15
B15
A14
B14
+1.8V_NB_VDDLT18
VSSLT1(VSS)
VSSLT2(VSS)
VSSLT3(VSS)
VSSLT4(VSS)
VSSLT5(VSS)
VSSLT6(VSS)
VSSLT7(VSS)
C14
D15
C16
C18
C20
E20
C22
LVDS_DIGON(PCE_TCALRP)
LVDS_BLON(PCE_RCALRP)
LVDS_ENA_BL(PW M_GPIO2)
E9
F7
G12
SCL:15mA
L39
1.4A/220ohm_6
L38
1.4A/220ohm_6
C
+1.8V
15mils
15mils
C377
0.1U/10V_4
SCL:0.3A
CRB:0.22A
C369
4.7U/6.3V_6
LVDS or DVI/ HDMI Digital power
MIS.
INT_LVDS_DIGON <16>
INT_LVDS_PWM <16>
INT_LVDS_BLON <16>
TMDS_HPD(NC)
HPD(NC)
D9
D10
SUS_STAT#(PW M_GPIO5)
D12
THERMALDIODE_P
THERMALDIODE_N
AE8
AD8
TESTMODE
LVDS POWER
LVDS BL_PWM
LVDS BL_EN
Confirmed with AMD Horace
LVDS_DIGON/ LVDS_BLON/ LVDS_ENA_BL need to be
pulled down with 4.7K
B
INT_HDMI_HPD
<17>
T26
SUS_STAT#_NB
R156
SPM@0/J_4
SUS_STAT# <11>
D13 TEST_EN
AUX_CAL(NC)
R334
1.8K/J_4
RS880M
A
R142
BOM@3K/J_4
R137
SPM@3K/J_4
+3V
Selects Loading of STRAPS from EPROM
1 : Bypass the loading of EEPROM straps and use Hardware Default Values
0 : I2C Master can load strap values from EEPROM if connected, or use
default values if not connected
Quanta Computer Inc.
+3V
PROJECT : ZH9
Size
EEPROM not implemented
R153
4.7K/J_4
SUS_STAT#_NB
4
3
Document Number
Rev
4A
RS880-SYSTEM I/F 3/4
Date:
5
<16>
<16>
<16>
<16>
<16>
<16>
Support Vari-Bright
I
T2
T1
STRP_DATA
*0/short_4
TXOUT_U0P(NC)
TXOUT_U0N(NC)
TXOUT_U1P(PCIE_RESET_GPIO3)
TXOUT_U1N(PCIE_RESET_GPIO2)
TXOUT_U2P(NC)
TXOUT_U2N(NC)
TXOUT_U3P(PCIE_RESET_GPIO5)
TXOUT_U3N(NC)
TXLOUT0+
TXLOUT0TXLOUT1+
TXLOUT1TXLOUT2+
TXLOUT2-
DFT_GPIO1: LOAD_EEPROM_STRAPS
Selects if Memory SIDE PORT is available or not
1 = Memory Side port Not available
0 = Memory Side port available
<BOM NOTE>
w/ sideport: R142 non-stuff
w/o sideport: R142 stuff
A12
D14
B12
R144
STRP_DATA
1 = 0.95V
0 = 1.1 V
*3K/J_4
RS880M: Enables Side port memory
A
R139
DAC_RSET(PW M_GPIO1)
[email protected]/J_4
<10> CLK_SBLINKP
<10> CLK_SBLINKN
<29> +NB_CORE_ON
G14
NB_RST#_IN
NB_PWRGD_IN
NB_LDT_STOP#
NB_ALLOW_LDTSTOP
T27
T18
Enables the Test Debug Bus using GPIO.
1 = Disable
0 = Enable
DAC_HSYNC(PW M_GPIO4)
DAC_VSYNC(PW M_GPIO6)
DAC_SDA(PCE_TCALRN)
DAC_SCL(PCE_RCALRN)
[email protected]/J_4
<16> LCD_DATA
<16> LCD_CLK
<17> HDMI_DDC_DATA
<17> HDMI_DDC_CLK
STRAP_DEBUG_BUS_GPIO_ENABLEb
A11
B11
E8
F8
VDDA18PCIEPLL1
VDDA18PCIEPLL2
CLK_NBGFXP
CLK_NBGFXN
<20091009(A1A)_46105_rs880_scl_nda_1.04>
Pulled 4.7K 5% low to GND when internal CLK Gen. used
(For GFX Clock Pair)
RED(DFT_GPIO0)
REDb(NC)
GREEN(DFT_GPIO1)
GREENb(NC)
BLUE(DFT_GPIO3)
BLUEb(NC)
TXOUT_L0P(NC)
TXOUT_L0N(NC)
TXOUT_L1P(NC)
TXOUT_L1N(NC)
TXOUT_L2P(NC)
TXOUT_L2N(DBG_GPIO0)
TXOUT_L3P(NC)
TXOUT_L3N(DBG_GPIO2)
PART 3 OF 6
D7
E7
2.2U/6.3V_6
<10> NB_RST#_IN
<11> NB_PWRGD
CRB:0.1A@all +1.8V PLLs
715/F_6
+1.1V_NB_PLLVDD
+1.8V_NB_PLLVDD18
2.2U/6.3V_6
2.2U/6.3V_6
G18
G17
E18
F18
E19
F19
15mils
SCL:65mA
C155
C146
22U/6.3V_8
HT LINK PLL power
<16> CRT_HSYNC
<16> CRT_VSYNC
<16> CRT_SDA
<16> CRT_SCL
R325
CRB:0.23A@all +1.1V PLLs
C_Pr(DFT_GPIO5)
Y(DFT_GPIO2)
COMP_Pb(DFT_GPIO4)
140/F_4
<16>
CRT_B
Confirmed with AMD FAE Reden
Follow Bimini Rev1.2 for PLLVDD18 to prevent noise coupling
Change L8203 from bead to 3.9ohm
<20100323(RAMP)_Follow 46105_rs880_scl_nda_1.05>
Change R121 from 3.9ohm(CS-3902JB00) to bead(CX8PG221003)
and C159 from 4.7uF(CH5471M9907) to 2.2uF(CH52201K991)
C
E17
F17
F15
C499
2.2U/6.3V_6
*0/J_4
R134
AVDD1(NC)
AVDD2(NC)
AVDDDI(NC)
AVSSDI(NC)
AVDDQ(NC)
AVSSQ(NC)
A22
B22
A21
B21
B20
A20
A19
B19
R150
SCL:4mA
L41
F12
E12
F14
G15
H15
H14
4.7K/J_4
+1.8V
NB_LDT_STOP#
4
D
C470
1U/6.3V_4
CRT/TVOUT
3
C162
2.2U/6.3V_6
DAC Bandgap Reference power
<10> ALLOW_LDTSTOP
15mils
+1.8V_NB_AVDDDI
1.4A/220ohm_6
<20100319(RAMP)>
Add C415,C470,C499(1uF), for monitor noise issue.
R354
300/J_4
1U/6.3V_4
SCL:20mA
R336
SCL:110mA
CRB:125mA
C415
PLL PWR
LVTM
+1.8V
DAC Digital power
+ U18
Open
Drain
2
<4,10> CPU_LDT_STOP#
+3V_NB_AVDD
1.4A/220ohm_6
<20100310(C3A)>
C163
Change R336 from 0ohm(CS00002JB38) to bead(CX8PG221003) and C162 from
0.1uF(CH4102K1B03) to 2.2uF(CH52201K991), for monitor noise issue.
2.2U/6.3V_6
PM
5
R353
*300/J_4
1
CLOCKs
D
2
15mils
L14
DAC Analog power
<20100303(C3A)>
Change R354 from CS22202JB18(2.2K) to
CS13002JB20(300ohm ) depend on the
measurement result, for LDTSTP# skew
issue.
C408
0.1U/10V_4
3
+3V
Note:Regarding LDT_STOP# signal,It's required within
40ns skew for both assertion and de-assertion between
NB and CPU.
+1.8V
+1.8V
2
Sunday, March 28, 2010
Sheet
1
8
of
40
3
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
VSS27
VSS28
VSS29
VSS30
VSS31
VSS32
VSS33
VSS34
L12
M14
N13
P12
P15
R11
R14
T12
U14
U11
U15
V12
W11
W15
AC12
AA14
Y18
AB11
AB15
AB17
AB19
AE20
AB21
K11
VSSAHT1
VSSAHT2
VSSAHT3
VSSAHT4
VSSAHT5
VSSAHT6
VSSAHT7
VSSAHT8
VSSAHT9
VSSAHT10
VSSAHT11
VSSAHT12
VSSAHT13
VSSAHT14
VSSAHT15
VSSAHT16
VSSAHT17
VSSAHT18
VSSAHT19
VSSAHT20
VSSAHT21
VSSAHT22
VSSAHT23
VSSAHT24
VSSAHT25
VSSAHT26
VSSAHT27
A25
D23
E22
G22
G24
G25
H19
J22
L17
L22
L24
L25
M20
N22
P20
R19
R22
R24
R25
H20
U22
V19
W22
W24
W25
Y21
AD25
+1.1V
35mils
*0/short_6
C172
4.7U/6.3V_6
+1.1V_NB_VDDHT
C168
0.1U/10V_4
C164
0.1U/10V_4
C169
0.1U/10V_4
40mils
HT LINK RX I/O power
R113
SCL:0.7A
*0/short_6
C152
4.7U/6.3V_6
PCIe TX Stage I/O power
+1.8V
C150
0.1U/10V_4
C147
0.1U/10V_4
L17
C156
0.1U/10V_4
20mils
+1.1V_NB_VDDHTTX
*0/short_6
C192
4.7U/6.3V_6
B
+1.1V_NB_VDDHTRX
SCL:0.4A
CRB:0.68A
R152
RX881
RS880
PIN NAME
RX881
VDDHT
+1.1V
+1.1V
IOPLLVDD
+1.1V
+1.1V
VDDHTRX
+1.1V
+1.1V
AVDD
GND
+3.3V
VDDHTTX
+1.2V
+1.2V
AVDDDI
GND
+1.8V
VDDA18PCIE
+1.8V
+1.8V
AVDDQ
GND
+1.8V
VDD18
+1.8V
+1.8V
PLLVDD
GND
+1.1V
VDD18_MEM
GND
+1.8V
PLLVDD18
GND
+1.8V
VDDPCIE
+1.1V
+1.1V
VDDA18PCIEPLL
+1.8V
+1.8V
VDDC
+1.1V
+0.95V~+1.1V
VDDA18HTPLL
+1.8V
+1.8V
VDD_MEM
GND
+1.8V/1.5V
VDDLTP18
GND
+1.8V
VDD33
+3.3V
+3.3V
VDDLT18
GND
+1.8V
IOPLLVDD18
+1.8V
+1.8V
VDDLT33
NC
NC
C190
0.1U/10V_4
C191
0.1U/10V_4
C188
0.1U/10V_4
SCL:0.7A
CRB:0.64A
25mils
1.4A/220ohm_6
+1.8V_NB_VDDA18PCIE
C213
4.7U/6.3V_6
C211
4.7U/6.3V_6
C197
0.1U/10V_4
C207
0.1U/10V_4
C187
0.1U/10V_4
SCL:10mA
CRB:5mA
I/O Transform power
Memory I/O Transform
C177
0.1U/10V_4
C203
0.1U/10V_4
15mils
+1.8V
R157
*0/short_6
+1.8V_NB_VDD18
+1.8V
R367
SPM@0/J_6
+1.8V_NB_VDD18_MEM
CRB:25mA
VDDHT_1
VDDHT_2
VDDHT_3
VDDHT_4
VDDHT_5
VDDHT_6
VDDHT_7
H18
G19
F20
E21
D22
B23
A23
VDDHTRX_1
VDDHTRX_2
VDDHTRX_3
VDDHTRX_4
VDDHTRX_5
VDDHTRX_6
VDDHTRX_7
AE25
AD24
AC23
AB22
AA21
Y20
W 19
V18
U17
T17
R17
P17
M17
J10
P10
K10
M10
L10
W9
H9
T10
R10
Y9
AA9
AB9
AD9
AE9
U10
F9
G9
AE11
AD11
PART 5/6
VDDHTTX_1
VDDHTTX_2
VDDHTTX_3
VDDHTTX_4
VDDHTTX_5
VDDHTTX_6
VDDHTTX_7
VDDHTTX_8
VDDHTTX_9
VDDHTTX_10
VDDHTTX_11
VDDHTTX_12
VDDHTTX_13
VDDA18PCIE_1
VDDA18PCIE_2
VDDA18PCIE_3
VDDA18PCIE_4
VDDA18PCIE_5
VDDA18PCIE_6
VDDA18PCIE_7
VDDA18PCIE_8
VDDA18PCIE_9
VDDA18PCIE_10
VDDA18PCIE_11
VDDA18PCIE_12
VDDA18PCIE_13
VDDA18PCIE_14
VDDA18PCIE_15
VDDPCIE_1
VDDPCIE_2
VDDPCIE_3
VDDPCIE_4
VDDPCIE_5
VDDPCIE_6
VDDPCIE_7
VDDPCIE_8
VDDPCIE_9
VDDPCIE_10
VDDPCIE_11
VDDPCIE_12
VDDPCIE_13
VDDPCIE_14
VDDPCIE_15
VDDPCIE_16
VDDPCIE_17
VDDC_1
VDDC_2
VDDC_3
VDDC_4
VDDC_5
VDDC_6
VDDC_7
VDDC_8
VDDC_9
VDDC_10
VDDC_11
VDDC_12
VDDC_13
VDDC_14
VDDC_15
VDDC_16
VDDC_17
VDDC_18
VDDC_19
VDDC_20
VDDC_21
VDDC_22
VDD_MEM1(NC)
VDD_MEM2(NC)
VDD_MEM3(NC)
VDD_MEM4(NC)
VDD_MEM5(NC)
VDD_MEM6(NC)
VDDG18_1(VDD18_1)
VDDG18_2(VDD18_2)
VDD18_MEM1(NC)
VDD18_MEM2(NC)
VDDG33_1(NC)
VDDG33_2(NC)
A6
B6
C6
D6
E6
F6
G7
H8
J9
K9
M9
L9
P9
R9
T9
V9
U9
AE10
AA11
Y11
AD10
AB10
AC10
R163
*0/short_8
R160
C206
0.1U/10V_4
C198
0.1U/10V_4
C199
1U/10V_4
C210
1U/10V_4
+1.1V
PCIe Main I/O power
*0/short_6
C212
4.7U/6.3V_6
SCL:10A
CRB:7.6A
Core Logic power
+NB_CORE
+0.95V or +1.1V
C196
0.1U/10V_4
C166
0.1U/10V_4
C170
0.1U/10V_4
C195
0.1U/10V_4
C208
10U/6.3V_8
B
C173
0.1U/10V_4
C200
0.1U/10V_4
C175
0.1U/10V_4
C209
10U/6.3V_8
Memory I/O
SCL:100mA
+1.5V_NB_VDD_MEM
C214
[email protected]/10V_4
C219
[email protected]/10V_4
R179
C217
[email protected]/10V_4
C215
[email protected]/10V_4
+3V_NB_VDD33
C167
0.1U/10V_4
R159
*0/short_6
C194
0.1U/10V_4
+3V
SCL:60mA
CRB:60mA
C416
BOM@1U/10V_4
SPM@0/J_6
+1.5V
C226
[email protected]/6.3V_6
For Side Port
+1.5V for DDR3
+1.8V for DDR2
If not support side port,
connect to GND.
15mils
+3.3V I/O power
H11
H12
RS880M
C193
1U/10V_4
C
+1.1V_NB_VDDPCIE
550mils
K12
J14
U16
J11
K15
M12
L14
L11
M13
M15
N12
N14
P11
P13
P14
R12
R15
T11
T15
U12
T14
J16
D
SCL:2.5A
CRB:1.1A
130mils
U20E
J17
K16
L16
M16
P16
R16
T16
RS880
l.c
om
SCL:0.6A
POWER
R145
HT LINK Digital I/O power
+1.1V
PIN NAME
CRB:0.68A
C
HT LINK TX I/O power
1
RX881/RS880 POWER DIFFERENCE TABLE
GROUND
D
PART 6/6
VSSAPCIE1
VSSAPCIE2
VSSAPCIE3
VSSAPCIE4
VSSAPCIE5
VSSAPCIE6
VSSAPCIE7
VSSAPCIE8
VSSAPCIE9
VSSAPCIE10
VSSAPCIE11
VSSAPCIE12
VSSAPCIE13
VSSAPCIE14
VSSAPCIE15
VSSAPCIE16
VSSAPCIE17
VSSAPCIE18
VSSAPCIE19
VSSAPCIE20
VSSAPCIE21
VSSAPCIE22
VSSAPCIE23
VSSAPCIE24
VSSAPCIE25
VSSAPCIE26
VSSAPCIE27
VSSAPCIE28
VSSAPCIE29
VSSAPCIE30
VSSAPCIE31
VSSAPCIE32
VSSAPCIE33
VSSAPCIE34
VSSAPCIE35
VSSAPCIE36
VSSAPCIE37
VSSAPCIE38
VSSAPCIE39
VSSAPCIE40
U20F
2
AE14
D11
G8
E14
E15
J15
J12
K14
M11
L15
4
A2
B1
D3
D5
E4
G1
G2
G4
H7
J4
R7
L1
L2
L4
L7
M6
N4
P6
R1
R2
R4
V7
U4
V8
V6
W1
W2
W4
W7
W8
Y6
AA4
AB5
AB1
AB7
AC3
AC4
AE1
AE4
AB2
5
Without side-port: Connected to GND plane.
A
ai
A
tm
<BOM NOTE>
w/ sideport: C214:CH4102K1B03 ; C416:CH5102K9B06
w/o sideport: C214,C416:CS00002JB38(0ohm)
f@
ho
Quanta Computer Inc.
Rev
4A
xa
Document Number
in
PROJECT : ZH9
Size
Date:
5
4
3
2
he
RS880-POWER 4/4
Sunday, March 28, 2010
Sheet
1
9
of
40
4
3
2
1
PCIE_RST#: Reset PCIe Slot/Device (PCIe interface from SB)
A_RST#: Reset NB, MXM, EC, PCIe Slot/Device (PCIe interface from NB)
U5A
A_TX0P
A_TX0N
A_TX1P
A_TX1N
A_TX2P
A_TX2N
A_TX3P
A_TX3N
A_TXP0
A_TXN0
A_TXP1
A_TXN1
A_TXP2
A_TXN2
A_TXP3
A_TXN3
AE24
AE23
AD25
AD24
AC24
AC25
AB25
AB24
A_RX0P
A_RX0N
A_RX1P
A_RX1N
A_RX2P
A_RX2N
A_RX3P
A_RX3N
A_TXP0
A_TXN0
A_TXP1
A_TXN1
A_TXP2
A_TXN2
A_TXP3
A_TXN3
R350
R349
+1.1V_SB_VDDAN_11_PCIE
590/F_4
2K/F_4
PCIE_CALRP_SB AD29
PCIE_CALRN_SB AD28
AA28
AA29
Y29
Y28
Y26
Y27
W28
W29
<20100325(RAMP)>
Change RP1~RP4,RP6~RP8 to shortpad.
C
to NB for A-LINK/PCIe REF CLK
<8> CLK_SBLINKP
<8> CLK_SBLINKN
to NB Display Eng
<8> NB_REFCLK_P
<8> NB_REFCLK_N
<8> CLK_NB_HTREFP
<8> CLK_NB_HTREFN
<4> CLK_CPU_BCLKP
<4> CLK_CPU_BCLKN
<Layout note>
Share pad with other resisters
and close to external CLK Gen.
RP7
RP2
RP1
RP8
AA22
Y21
AA25
AA24
W23
V24
W24
W25
<23> CLK_PCIE_MNC_P
<23> CLK_PCIE_MNC_N
RP4
CLK_SBSRCP
CLK_SBSRCN
M23
P23
<21> CLK_PCIE_LANP
<21> CLK_PCIE_LANN
to LAN
RP6
U29
U28
SB_NB_REFCLKP
SB_NB_REFCLKN
4
2
3 *ICK@0/short__4P2R
1
SB_NB_HTCLKP
SB_NB_HTCLKN
T26
T27
NB_HT_CLKP
NB_HT_CLKN
4
2
3 *ICK@0/short__4P2R
1
SB_CPU_CLKP
SB_CPU_CLKN
V21
T21
CPU_HT_CLKP
CPU_HT_CLKN
3 *3G@ICK@0/short__4P2R SB_MNC_CLKP
SB_MNC_CLKN
1
4
2
L29
L28
1 *ICK@0/short__4P2R
3
2
4
SB_LAN_CLKP
SB_LAN_CLKN
M29
M28
L24
L23
P25
M25
P29
P28
N26
N27
to LAN chip 25MHz
<20100310(C3A)>
Non-Stuff R345. (14M_25M_48M_OSC is S0 plane,
doesn't support WoL.)
*ICK@22/J_4
SB_MPC_CLKP
SB_MPC_CLKN
T29
T28
SB_CLK_25M_LAN L25
SLT_GFX_CLKP
SLT_GFX_CLKN
GPP_CLK0P
GPP_CLK0N
AD0/GPIO0
AD1/GPIO1
AD2/GPIO2
AD3/GPIO3
AD4/GPIO4
AD5/GPIO5
AD6/GPIO6
AD7/GPIO7
AD8/GPIO8
AD9/GPIO9
AD10/GPIO10
AD11/GPIO11
AD12/GPIO12
AD13/GPIO13
AD14/GPIO14
AD15/GPIO15
AD16/GPIO16
AD17/GPIO17
AD18/GPIO18
AD19/GPIO19
AD20/GPIO20
AD21/GPIO21
AD22/GPIO22
AD23/GPIO23
AD24/GPIO24
AD25/GPIO25
AD26/GPIO26
AD27/GPIO27
AD28/GPIO28
AD29/GPIO29
AD30/GPIO30
AD31/GPIO31
CBE0#
CBE1#
CBE2#
CBE3#
FRAME#
DEVSEL#
IRDY#
TRDY#
PAR
STOP#
PERR#
SERR#
REQ0#
REQ1#/GPIO40
REQ2#/CLK_REQ8#/GPIO41
REQ3#/CLK_REQ5#/GPIO42
GNT0#
GNT1#/GPO44
GNT2#/GPO45
GNT3#/CLK_REQ7#/GPIO46
CLKRUN#
LOCK#
INTE#/GPIO32
INTF#/GPIO33
INTG#/GPIO34
INTH#/GPIO35
GPP_CLK1P
GPP_CLK1N
GPP_CLK2P
GPP_CLK2N
GPP_CLK3P
GPP_CLK3N
GPP_CLK4P
GPP_CLK4N
GPP_CLK5P
GPP_CLK5N
GPP_CLK6P
GPP_CLK6N
LPCCLK0
LPCCLK1
LAD0
LAD1
LAD2
LAD3
LFRAME#
LDRQ0#
LDRQ1#/CLK_REQ6#/GPIO49
SERIRQ/GPIO48
GPP_CLK7P
GPP_CLK7N
GPP_CLK8P
GPP_CLK8N
ALLOW_LDTSTP/DMA_ACTIVE#
PROCHOT#
LDT_PG
LDT_STP#
LDT_RST#
25M_X1
27P/50V_4
L26
Y4
25MHz-SB820M
R355
1M/J_4
25M_X2
L27
27P/50V_4
PCI_CLK1
PCI_CLK2
PCI_CLK3
PCI_CLK4
PCIRST#_L
V2
AA1
AA4
AA3
AB1
AA5
AB2
AB6
AB5
AA6
AC2
AC3
AC4
AC1
AD1
AD2
AC6
AE2
AE1
AF8
AE3
AF1
AG1
AF2
AE9
AD9
AC11
AF6
AF4
AF3
AH2
AG2
AH3
AA8
AD5
AD8
AA10
AE8
AB9
AJ3
AE7
AC5
AF5
AE6
AE4
AE11
AH5
AH4
AC12
AD12
AJ5
AH6
AB12
AB11
AD7
R69
BOARD_ID0
BOARD_ID1
BOARD_ID2
BOARD_ID3
BOARD_ID4
PCIRST#
33/J_4
C98
R56
33/J_4
<14>
<14>
<14>
<14>
25M_X1
25M_X2
10p/50V_4
R59
<20100119(B2A)_Bimini Rev1.4>
Non-stuff U21,C429,C428,R372,R300
(Nile doesn't support +1.05V for
DDR3-1333)
SPM@10K/J_4
BOM@10K/J_4
BOARD_ID1 R295
R283
BOM@10K/J_4
BOARD_ID2 R284
BOM@10K/J_4
R63
*10K/J_4
BOARD_ID3 R64
*10K/J_4
R302
*10K/J_4
BOARD_ID4 R303
*10K/J_4
*0/J_4
SB_GPIO_PCIE_RST#
<11>
U4
TC7SH08FU
AD23
AD24
<14>
<14>
AD25
AD26
AD27
<14>
<14>
<14>
D
*0/J_4
Model
SAM DDR3-800 1Gb K4W1G1646E-HC12
HYN DDR3-800 1Gb H5TQ1G63BFR-12C
ATI DDR3-800 1Gb 23EY2387MA12-SZ
R296
AD23
AD24
AD25 R300
AD26
AD27
A_RST#_SB <25>
1
150P/50V_4
BOARD_ID0 R77
*10K/J_4
A_RST#_SB
2
4
C81
MINI-PCIE
LAN chip
Card reader
For VDDR
R78
A_RST#_AND
<21,23,24> PLTRST#
PCIRST# <23>
<BOM Note>
ID0/1/2 P/N
000
AKD5LGGT506
001
AKD5LZGTW04
010
AKD5LGGT700
+3V
0.1u/10V_4
5
T64
The Nile VDDR should be 0.9V
all the time. The 1.05V is only
for DDR3_1333 which is not
supported on Nile.
+3V
C429
*0.1U/10V_4
BOM@10K/J_4
MEM_1V5 is for gating the glitch on VDDR_1.2_EN
2
<12> MEM_1V5
VDDR_1.2_EN
4 R372
VDDR_1.2_EN:
1 : VDDR =1.05V
0: VDDR = 0.90V (Default)
VDDR_1.2_EN
R95
*2.2K/J_4
SB820_MEMHOT#
1
R94
*2.2K/J_4
Q10
*MMBT3904
3
VDDR_1.2_EN="0" is for DDRIII-1066, VDDR=0.9V
VDDR_1.2_EN="1" is for DDRIII-1333, VDDR=1.05V
*33/J_4
VDDR_OPT <33>
1
+3V
C428
*150P/50V_4
U21
*TC7SH08FU
R368
*0/J_4
CPU_MEMHOT# <11,15>
C
RTC(RTC)
VCCRTC
D19
+3VPCU
CH500H-40
D20
VCCRTC_4
CH500H-40
INT_CLKREQ_MPC# R293
*0/short_4
CLKREQ_MPC#
<23>
CLKRUN#
<25>
From MINI PCIE 1
G1
*SHORT_PAD
T74
T76
R202
1K/J_4
AJ6
AG6
AG4
AJ4
R97
*0/short_4
20MIL
H24
H25
J27
J26
H29
H28
G28
J25
AA18
AB19
LPC_CLK0
LPC_CLK1
LAD0
LAD1
LAD2
LAD3
LFRAME#
LDRQ0#_SB
LDRQ1#_SB
SERIRQ
G21
H21
K19
G22
J24
ALLOW_LDTSTOP
CPU_PROCHOT#
CPU_PWRGD
CPU_LDT_STOP#
CPU_LDT_RST#
C1
RTC_X1
C2
RTC_X2
D2
B2
B1
RTC_CLK
INTRUDER_ALERT#
VCCRTC_SB
R342
R141
LAD0
LAD1
LAD2
LAD3
LFRAME#
<23,25>
<23,25>
<23,25>
<23,25>
<23,25>
SERIRQ
<25>
1
3
Q12
MMBT3904
LPC_CLK0 <14>
LPC_CLK1 <14>
LCLK_EC <25>
LCLK_DEBUG <23>
22/J_4
22/J_4
+5VPCU
20MIL
VCCRTC_3
VCCRTC_2
R213
8.06K/F_4
VCCRTC_1
R219
8.06K/F_4
B
R = (5V - 0.2V-2V)/0.2mA = 14k
R220
68.1K/F_4
BT1
RTC BATT
<20100303(C3A)>
Delete CN5 and Add BT1, for Battery SMT type.
<20100310(C3A)>
Swap BT1's pin, for pin define error
2
1
T85
T83
R221
150K/F_4
<BOM Note>
RTC BATTERY
AHL03001033 : JHT (18mAh)
AHL03001032 : MAT (17mAh)
AHL03001035 : FDK (15mAh)
ALLOW_LDTSTOP <8>
CPU_PROCHOT# <4>
CPU_PWRGD <4>
CPU_LDT_STOP# <4,8>
CPU_LDT_RST# <4>
RTC_X1
32K_X2
RTCCLK
INTRUDER_ALERT#
VDDBT_RTC_G
SB820M
C412
PCI_CLK0
PCI_CLK1
PCI_CLK2
PCI_CLK3
PCI_CLK4
14M_25M_48M_OSC
32K_X1
C411
2
A
R345
<21> CLK_25M_LAN
<20100129(B2A)>
Stuff R345. (CLK for LAN from crystal
change to internal CLK.)
3 *ICK@0/short__4P2R
1
4
2
NB_DISP_CLKP
NB_DISP_CLKN
1
to MINI PCIE 1
RP3
PCIE_RCLKP/NB_LNK_CLKP
PCIE_RCLKN/NB_LNK_CLKN
3 *ICK@0/short__4P2R
1
T25
V25
<23> CLK_PCIE_MPC_P
<23> CLK_PCIE_MPC_N
GPP_RX0P
GPP_RX0N
GPP_RX1P
GPP_RX1N
GPP_RX2P
GPP_RX2N
GPP_RX3P
GPP_RX3N
4
2
N29
N28
B
GPP_TX0P
GPP_TX0N
GPP_TX1P
GPP_TX1N
GPP_TX2P
GPP_TX2N
GPP_TX3P
GPP_TX3N
3 *ICK@0/short__4P2R
1
4
2
V23
T23
to MINI PCIE 2
PCIE_CALRP
PCIE_CALRN
PCIRST#
W2
W1
W3
W4
Y1
3
AD26
AD27
AC28
AC29
AB29
AB28
AB26
AB27
PCICLK0
PCICLK1/GPO36
PCICLK2/GPO37
PCICLK3/GPO38
PCICLK4/14M_OSC/GPO39
5
A_RXP0_C
A_RXN0_C
A_RXP1_C
A_RXN1_C
A_RXP2_C
A_RXN2_C
A_RXP3_C
A_RXN3_C
C80
Part 1 of 5
3
<7>
<7>
<7>
<7>
<7>
<7>
<7>
<7>
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
SB800
PCIE_RST#
A_RST#
1
C179
C180
C182
C181
C183
C184
C186
C185
A_RXP0
A_RXN0
A_RXP1
A_RXN1
A_RXP2
A_RXN2
A_RXP3
A_RXN3
P1
L1
2
D
33/J_4 A_RST#_SB_C
R89
2
PLACE THESE PCIE AC COUPLING
CAPS CLOSE TO SB820
<7>
<7>
<7>
<7>
<7>
<7>
<7>
<7>
150P/50V_4
PCI INTERFACE
A_RST#
LPC
C102
*0/short_4
PCI CLKS
*0/short_4
R65
CPU
R73
RTC
A_RST#_SB
PCI EXPRESS INTERFACES
<8> NB_RST#_IN
EC
CLOCK GENERATOR
NB
+3V_S5
For AMD RST
2
5
20MIL
Y2
RTC_CLK <25>
T62
R93
510/J_4 VCCRTC
RTC_X2
C116
C115
*0.1U/10V_4
2
3
1
4
INTRUDER_ALERT# Left not connected (Southbridge
has 50-kohm internal pull-up to VBAT).
20M/J_6
1U/10V_4
IC CTRL(605P)SB820M 218-0697014(FCBGA)
P/N : AJ069700T01
C111
18P/50V_4
<20100303(C3A)>
Change C411,C412 from CH02206JB08(22pF) to CH02706JB06(27pF), for Y4.
A
<20100303(C3A)>
Change C93,C111 from CH02206JB08(22pF) to CH01806JB07(18pF), for Y2.
32.768KHZ
R72
Quanta Computer Inc.
C93
18P/50V_4
PROJECT : ZH9
Size
Document Number
Rev
4A
SB820-PCIE/CPU/LPC 1/5
Date:
5
4
3
2
Sunday, March 28, 2010
Sheet
1
10
of
40
5
+3V_S5
4
3
2
1
NC only ,Can't be install
R100
*2.2K/J_4 SB_TEST0
R98
*2.2K/J_4 SB_TEST1
R280
*2.2K/J_4 SB_TEST2
<20100129(B2A)>
Stuff R110. (CLK for Cardreader from crystal
change to internal CLK.)
<25>
<25>
EC_SMI#
EC_SCI#
SYS_RST#
T13
R338
2.2K/J_4 SB_SCLK0
R335
2.2K/J_4 SB_SDATA0
<21,23> PCIE_WAKE#
C
10K/J_4
10K/J_4
SB_SCLK1
SB_SDATA1
R133
R337
10K/J_4
10K/J_4
SB_SCLK2
SB_SDATA2
R136
R148
10K/J_4
10K/J_4
SB_SCLK3
SB_SDATA3
RSMRST#
<25> EC_RSMRST#
SMBUS1~3 is +3.3V_S5 domain
If SMBUS and GPIO not implemented
10K PU to +3V_S5 or 10K PD
R279
R92
CPU_THERMTRIP#
NB_PWRGD
<4> CPU_THERMTRIP#
<8> NB_PWRGD
<10> SB_GPIO_PCIE_RST#
<23> CLKREQ_MNC#
R341
*0/short_4
G1
SB_GPIO_PCIE_RST#
INT_CLKREQ_MNC#
From MINI PCIE 2
<19> SB_BEEP
<15,23> SB_SCLK0
<15,23> SB_SDATA0
From LAN
SB_SCLK0
SB_SDATA0
SB_SCLK1
SB_SDATA1
*0/short_4 INT_CLKREQ_LAN#
R333
<21> CLKREQ_LAN#
T10
T19
R281
<6> SP_DDR3_RST#
LLB#
SHUTDOWN#
SPM@0/J_4
<20091202(A1A)_Confirm with AMD's Horace>
IDLEEXIT#(Multi function of Pin AA20) is used for server CPU.
AD19
AA16
AB21
AC18
AF20
AE19
AF19
AD22
AE22
F5
F4
AH21
AB18
E1
AJ21
H4
D5
D7
G5
K3
AA20
SB800
A10
USB_RCOMP
G19
USB_RCOMP_SB
J10
H11
USB_FSD13P
USB_FSD13N
H9
J8
USB_FDS12P
USB_FSD12N
300/J_4
<20>
NB_PWRGD
<20>
USBOC#R
USBOC#L
USBOC#67
R277
*0/J_4
R278
USBOC#0
*0/J_4
SB_JTAG_TDO
SB_JTAG_TCK
SB_JTAG_TDI
SB_JTAG_RST#
T73
T69
T68
T70
USB_HSD13P
USB_HSD13N
B12
A12
USB_HSD12P
USB_HSD12N
F11
E11
USB_HSD11P
USB_HSD11N
E14
E12
USB_HSD9P
USB_HSD9N
H3
D1
E4
D4
E8
F7
E7
F8
BLINK/USB_OC7#/GEVENT18#
USB_OC6#/IR_TX1/GEVENT6#
USB_OC5#/IR_TX0/GEVENT17#
USB_OC4#/IR_RX0/GEVENT16#
USB_OC3#/AC_PRES/TDO/GEVENT15#
USB_OC2#/TCK/GEVENT14#
USB_OC1#/TDI/GEVENT13#
USB_OC0#/TRST#/GEVENT12#
M3
N1
L2
M2
M1
M4
N2
P2
AZ_BITCLK
AZ_SDOUT
AZ_SDIN0/GPIO167
AZ_SDIN1/GPIO168
AZ_SDIN2/GPIO169
AZ_SDIN3/GPIO170
AZ_SYNC
AZ_RST#
USB OC
R340
USB_FSD0P/GPIO185
USB_FSD0N
USB_HSD10P
USB_HSD10N
+1.8V
R110
R332
ICK@22/J_4
CLK_48M_CR <24>
to CARD READER 48MHz
11.8K/F_6
D
USB_FSD1P/GPIO186
USB_FSD1N
RSMRST#
CLK_REQ4#/SATA_IS0#/GPIO64
CLK_REQ3#/SATA_IS1#/GPIO63
SMARTVOLT1/SATA_IS2#/GPIO50
CLK_REQ0#/SATA_IS3#/GPIO60
SATA_IS4#/FANOUT3/GPIO55
SATA_IS5#/FANIN3/GPIO59
SPKR/GPIO66
SCL0/GPIO43
SDA0/GPIO47
SCL1/GPIO227
SDA1/GPIO228
CLK_REQ2#/FANIN4/GPIO62
CLK_REQ1#/FANOUT4/GPIO61
IR_LED#/LLB#/GPIO184
SMARTVOLT2/SHUTDOWN#/GPIO51
DDR3_RST#/GEVENT7#
GBE_LED0/GPIO183
GBE_LED1/GEVENT9#
GBE_LED2/GEVENT10#
GBE_STAT0/GEVENT11#
CLK_REQG#/GPIO65/OSCIN
SB_CLK_48M_CR
USBCLK/14M_25M_48M_OSC
USB 1.1 USB MISC
To Clock gen/DDR/WLAN
GA20
KBRST#
PCI_PME#/GEVENT4#
RI#/GEVENT22#
SPI_CS3#/GBE_STAT1/GEVENT21#
SLP_S3#
SLP_S5#
PWR_BTN#
PWR_GOOD
SUS_STAT#
Part 4 of 5
TEST0
TEST1/TMS
TEST2
GA20IN/GEVENT0#
KBRST#/GEVENT1#
LPC_PME#/GEVENT3#
LPC_SMI#/GEVENT23#
GEVENT5#
SYS_RESET#/GEVENT19#
WAKE#/GEVENT8#
IR_RX1/GEVENT20#
THRMTRIP#/SMBALERT#/GEVENT2#
NB_PWRGD
USB 2.0
SCL0/SDATA0 is +3.3V_S0 domain
+3V
<25>
<25>
*0/short_4 SB_PWRGD
SUS_STAT#
SB_TEST0
SB_TEST1
SB_TEST2
R294
J2
K1
D3
F1
H1
F2
H5
G6
B3
C4
F6
AD21
AE21
K2
J29
H2
J1
H6
F3
J6
AC19
GPIO
<25>
SUSB#
<25>
SUSC#
<25> DNBSWON#
<25> ECPWROK
<8> SUS_STAT#
D
*0/J_4
ACPI / WAKE UP EVENTS
U5D
R91
<10,15> CPU_MEMHOT#
T9
J12
J14
T75
T77
OHCI (dev-20, fun-5)
T72
T71
Controller
OHCI0 (dev-18,
EHCI (dev-18,
OHCI0 (dev-19,
EHCI (dev-19,
OHCI0 (dev-22,
EHCI (dev-22,
fun-0)
fun-2)
fun-0)
fun-2)
fun-0)
fun-2)
D13
C13
USB+_SIM <23>
USB-_SIM <23>
USB_HSD7P
USB_HSD7N
G12
G14
USBP7+
USBP7-
<20>
<20>
USB_HSD6P
USB_HSD6N
G16
G18
USBP6+
USBP6-
<20>
<20>
D16
C16
USBP5+
USBP5-
<18>
<18>
BT
USB_HSD4P
USB_HSD4N
B14
A14
USBP4+
USBP4-
<23>
<23>
MNC
USB_HSD3P
USB_HSD3N
E18
E16
USBP3+
USBP3-
<16>
<16>
CCD
USB_HSD2P
USB_HSD2N
J16
J18
USBP2+
USBP2-
<23>
<23>
MPC
USB_HSD1P
USB_HSD1N
B17
A17
USBP1+
USBP1-
<24>
<24>
Card reader
A16
B16
USBP0+
USBP0-
<20>
<20>
CONN (Left)
USB_HSD0P
USB_HSD0N
mapping
0 - 4
0 - 4
5 - 9
5 - 9
10 - 14
10 - 14
A13
B13
USB_HSD8P
USB_HSD8N
USB_HSD5P
USB_HSD5N
Ports
Port
Port
Port
Port
Port
Port
MM-SIM
CONN (Lower Right)
CONN (Upper Right)
C
*10P/50V_4
C101
*10P/50V_4
33/J_4
ACZ_SYNC_AUDIO
R87
33/J_4
R88
*10K/J_4
R71
33/J_4
ACZ_SDIN0
+3V_S5
10K/J_4
10K/J_4
R286
10K/J_4
R83
10K/J_4
R282
10K/J_4
<19>
<20091030(A1A)_EMI's Suggest>
Add one 10pF to GND for BITCLK
ACZ_BITCLK_AUDIO <19>
ACZ_RST#_AUDIO <19>
ACZ_SDIN0 <19>
T1
T4
L6
L5
T9
U1
U3
T2
U2
T5
V5
P5
M5
P9
T7
P7
M7
P4
M9
V7
*10K/J_4
T17
T22
E23
E24
F21
G29
D27
F28
F29
E27
A
GBE_COL
GBE_CRS
GBE_MDCK
GBE_MDIO
GBE_RXCLK
GBE_RXD3
GBE_RXD2
GBE_RXD1
GBE_RXD0
GBE_RXCTL/RXDV
GBE_RXERR
GBE_TXCLK
GBE_TXD3
GBE_TXD2
GBE_TXD1
GBE_TXD0
GBE_TXCTL/TXEN
GBE_PHY_PD
GBE_PHY_RST#
GBE_PHY_INTR
PS2_DAT/SDA4/GPIO187
PS2_CLK/SCL4/GPIO188
SPI_CS2#/GBE_STAT2/GPIO166
FC_RST#/GPO160
PS2KB_DAT/GPIO189
PS2KB_CLK/GPIO190
PS2M_DAT/GPIO191
PS2M_CLK/GPIO192
KSO_0/GPIO209
KSO_1/GPIO210
KSO_2/GPIO211
KSO_3/GPIO212
KSO_4/GPIO213
KSO_5/GPIO214
KSO_6/GPIO215
KSO_7/GPIO216
KSO_8/GPIO217
KSO_9/GPIO218
KSO_10/GPIO219
KSO_11/GPIO220
KSO_12/GPIO221
KSO_13/GPIO222
KSO_14/GPIO223
KSO_15/GPIO224
KSO_16/GPIO225
KSO_17/GPIO226
B28
A27
B27
D26
A26
C26
A24
B25
A25
D24
B24
C24
B23
A23
D22
C22
A22
B22
A
Quanta Computer Inc.
SB820M
PROJECT : ZH9
4
3
Date:
Sunday, March 28, 2010
Rev
4A
ai
Document Number
2
tm
5
Size
ho
R90
R70
R84
B
f@
ACZ_RST#
ACZ_SDOUT_AUDIO <19>
C100
EC_PWM2 <14>
EC_PWM3 <14>
in
ACZ_BCLK
R86
33/J_4
G24
G25
E28
E29
D29
D28
C29
C28
xa
ACZ_SYNC
R85
KSI_0/GPIO201
KSI_1/GPIO202
KSI_2/GPIO203
KSI_3/GPIO204
KSI_4/GPIO205
KSI_5/GPIO206
KSI_6/GPIO207
KSI_7/GPIO208
SB_SCLK2
SB_SDATA2
SB_SCLK3
SB_SDATA3
he
ACZ_SDOUT
*10P/50V_4
D25
F23
B26
E26
F25
E22
F22
E21
l.c
om
ACZ_SYNC
ACZ_RST#
C99
SCL2/GPIO193
SDA2/GPIO194
SCL3_LV/GPIO195
SDA3_LV/GPIO196
EC_PWM0/EC_TIMER0/GPIO197
EC_PWM1/EC_TIMER1/GPIO198
EC_PWM2/EC_TIMER2/GPIO199
EC_PWM3/EC_TIMER3/GPIO200
EMBEDDED CTRL
To Azalia
EMBEDDED CTRL
B
GBE LAN
ACZ_BCLK
ACZ_SDOUT
ACZ_SDIN0
<14> ACZ_SDOUT
HD AUDIO
HD audio interface is +3V_S5 voltage
SB820-ACPI/GPIO/USB 2/5
Sheet
1
11
of
40
5
4
0.01U/25V_4
0.01U/16V_4
SATA_TXP0_C
SATA_TXN0_C
AH9
AJ9
C140
C137
0.01U/25V_4
0.01U/25V_4
SATA_RXN0_C
SATA_RXP0_C
AJ8
AH8
AH10
AJ10
AG10
AF10
AG12
AF12
AJ12
AH12
AH14
AJ14
AG14
AF14
AG17
AF17
C
PLACE SATA_CAL
RES VERY CLOSE
TO BALL OF SB820
AJ17
AH17
AJ18
AH18
AH19
AJ19
+1.1V_SB_VDDAN_11_SATA
R316
R315
To meet SB800 SCL1.02:
DNI SATA XTAL circuit's parts
1K/F_4 SATA_CALRP
931/F_4 SATA_CALRN
+3V
R304
AD11
*22P/50V_4
SATA_X1
AD16
SATA_RX0N
SATA_RX0P
FC_OE#/GPIOD145
FC_AVD#/GPIOD146
FC_WE#/GPIOD148
FC_CE1#/GPIOD149
FC_CE2#/GPIOD150
FC_INT1/GPIOD144
FC_INT2/GPIOD147
SATA_TX1P
SATA_TX1N
SATA_RX1N
SATA_RX1P
SATA_TX2P
SATA_TX2N
SATA_RX2N
SATA_RX2P
SATA_TX3P
SATA_TX3N
SATA_RX3N
SATA_RX3P
SATA_TX4P
SATA_TX4N
SATA_RX4N
SATA_RX4P
SATA_TX5P
SATA_TX5N
SATA_RX5N
SATA_RX5P
SATA_ACT#/GPIO67
R114
*1M/J_4
AC16
SATA_X2
SATA_X2
T45
T31
T39
AF28
AG29
AG26
AF27
AE29
AF29
AH27
T38
T37
T36
T43
T44
T32
T33
AJ27
AJ26
AH25
AH24
AG23
AH23
AJ22
AG21
AF21
AH22
AJ23
AF23
AJ24
AJ25
AG25
AH26
T42
T30
T29
T28
T23
T24
T21
T16
T80
T20
T25
T84
T34
T35
T40
T41
D
IF THERE IS NO IDE, TEST
POINTS FOR DEBUG BUS
IS MANDATORY
+3V
C
R105
R106
10K/J_4
VIN0/GPIO175
VIN1/GPIO176
VIN2/GPIO177
VIN3/GPIO178
VIN4/GPIO179
VIN5/GPIO180
VIN6/GBE_STAT3/GPIO181
VIN7/GBE_LED3/GPIO182
W5
W6
Y9
SB_PROCHOT#_C
Q11
MMBT3904
3
1
SB_PROCHOT# <4>
W7
V9
W8
B6
A6
A5
B5
C7
TEMPIN0
TEMPIN1
TEMPIN2
A3
B4
A4
C5
A7
B7
B8
A8
VIN0
VIN1
VIN2
VIN3
VIN4
VIN5
VIN6
VIN7
R109
R108
R103
10K/J_4
10K/J_4
10K/J_4
R107
10K/J_4
+3V_S5
THERM_ALERT# <4>
TEMP_COMM
R290
R289
R288
R102
R409
R298
R301
R297
10K/J_4
10K/J_4
10K/J_4
10K/J_4
10K/J_4
10K/J_4
10K/J_4
10K/J_4
<20100119(B2A)_Bimini Rev1.4>
Non-stuff R408 ; stuff R409
(Nile doesn't support VDDR = +1.05V for DDR3-1333)
VIN4 R408
*0/J_4
B
MEM_1V5 <10>
*22P/50V_4
J5
E2
K4
K9
G2
T67
T12
T11
T65
T66
SPI_DI/GPIO164
SPI_DO/GPIO163
SPI_CLK/GPIO162
SPI_CS1#/GPIO165
ROM_RST#/GPIO161
NC1
NC2
SPI ROM
C145
FANOUT0/GPIO52
FANOUT1/GPIO53
FANOUT2/GPIO54
TEMPIN0/GPIO171
TEMPIN1/GPIO172
TEMPIN2/GPIO173
TEMPIN3/TALERT#/GPIO174
TEMP_COMM
SATA_X1
AH28
AG28
AF26
10K/J_4
SATA_CALRP
SATA_CALRN
2
Y3
*25MHz-SATA
FC_ADQ0/GPIOD128
FC_ADQ1/GPIOD129
FC_ADQ2/GPIOD130
FC_ADQ3/GPIOD131
FC_ADQ4/GPIOD132
FC_ADQ5/GPIOD133
FC_ADQ6/GPIOD134
FC_ADQ7/GPIOD135
FC_ADQ8/GPIOD136
FC_ADQ9/GPIOD137
FC_ADQ10/GPIOD138
FC_ADQ11/GPIOD139
FC_ADQ12/GPIOD140
FC_ADQ13/GPIOD141
FC_ADQ14/GPIOD142
FC_ADQ15/GPIOD143
FANIN0/GPIO56
FANIN1/GPIO57
FANIN2/GPIO58
1
B
FC_CLK
FC_FBCLKOUT
FC_FBCLKIN
Part 2 of 5
10K/J_4
<22> SATALED#
C151
AB14
AA14
SB800
SATA_TX0P
SATA_TX0N
2
<22> SATA_RXN0
<22> SATA_RXP0
C141
C142
1
The flash controller function is NOT
supported by the SB820M.
FLASH
D
<22> SATA_TXP0
<22> SATA_TXN0
2
U5B
HW MONITOR
SATA HDD
PLACE SATA AC COUPLING
CAPS CLOSE TO SB820
SERIAL ATA
SATA PORT 0,1,2,3
can support AHCI
mode
3
G27
Y2
SB820M
A
A
Quanta Computer Inc.
PROJECT : ZH9
Size
Document Number
Rev
4A
SB820-SATA/HWM/SPI 3/5
Date:
5
4
3
2
Sunday, March 28, 2010
12
Sheet
1
of
40
5
4
3
2
1
PLACE ALL THE DECOUPLING CAPS ON
THIS SHEET CLOSE TO SB AS POSSIBLE.
U5C
AF22
AE25
AF24
AC22
1.4A/220ohm_6
C402
2.2U/6.3V_6
R344
*0/short_4
C401
*0.1U/10V_4
VDDIO_18_FC_1
VDDIO_18_FC_2
VDDIO_18_FC_3
VDDIO_18_FC_4
VDDRF_GBE_S
POWER
VDDIO_33_GBE_S
1
C387
0.1U/10V_4
C383
1U/10V_4
2
1
C389
0.1U/10V_4
2
C407
22U/6.3V_8
2
DCR=0.008Ω
Check
U26
V22
V26
V27
V28
V29
W 22
W 26
+1.1V_SB_VDDAN_11_PCIE
C
VDDAN_11_PCIE_1
VDDAN_11_PCIE_2
VDDAN_11_PCIE_3
VDDAN_11_PCIE_4
VDDAN_11_PCIE_5
VDDAN_11_PCIE_6
VDDAN_11_PCIE_7
VDDAN_11_PCIE_8
PCI EXPRESS
600mA 100mils
4A/42ohm_8
1
L44
VDDPL_33_PCIE
+1.1V_SB_VDDAN_11_PCIE
A-Link Express III/PCIe analog power
+1.1V
AE28
GBE LAN
43mA 15mils
+3V_SB_VDDPL_33_PCIE
*0/short_6
U5E
+1.1V
1
C338
10U/6.3V_8
Check
Y14
Y16
AB16
AC14
AE12
AE14
AF9
AF11
AF13
AF16
AG8
AH7
AH11
AH13
AH16
AJ7
AJ11
AJ13
AJ16
2
1
C353
1U/10V_4
2
1
C359
1U/10V_4
2
1
2
1
2
C346
0.1U/10V_4
R327
System Clock Gen analog/output power
1
4A/42ohm_8
+1.1V
DCR=0.008Ω
C399
C404
C178
ICK@1U/10V_4 ICK@1U/10V_4 ICK@22U/6.3V_8
2
C379
[email protected]/10V_4
2
C378
[email protected]/10V_4
1
L16
1
+1.1V_SB_VDDAN_11_CLK
K28
K29
J28
K26
J21
J20
K21
J22
<45484_sb800_dg_nda_1.02>
Not use interal CLK Gen: Connected to +1.1V directly.
V1
M10
A9
B10
K11
B9
D10
D12
D14
D17
E9
F9
F12
F14
F16
C9
G11
F18
D9
H12
H14
H16
H18
J11
J19
K12
K14
K16
K18
H19
Not support GBE: Connected to GND.
VDDCR_11_GBE_S_1
VDDCR_11_GBE_S_2
L7
L9
VDDIO_GBE_S_1
VDDIO_GBE_S_2
M6
P8
SATA PHY PLL power
L34
1.4A/220ohm_6
C374
1U/10V_4
+1.1VSUS_SB_VDDAN_11_USB_S
C337
2.2U/6.3V_6
*0/short_6
1
+3V_S5
2
1
2
1
2
R339
C332
2.2U/6.3V_6
S5 Core logic standby power
xx mA HD Audio I/O Power
20mils
M8
197mA
15mils
R348
C390
1U/10V_4
+3V_S5_SB_VDDIO_AZ_S
*0/short_6
+1.1V_S5
C391
1U/10V_4
VDDCR_11_USB_S_1
VDDCR_11_USB_S_2
A11
B11
VDDPL_33_SYS
M21
VDDPL_11_SYS_S
L22
F19
+3VSUS_SB_VDDPL_33_USB_S
17mA USB PHY PLL analog power
D6
+3V_S5_SB_VDDAN_33_HWM_S
5mA
VDDPL_33_USB_S
VDDAN_33_HW M_S
+1.1VSUS_SB_VDDCR_11_USB_S
Y4
EFUSE
D8
VSSAN_HW M
M19
VSSXL
P21
P20
M22
M24
M26
P22
P24
P26
T20
T22
T24
V20
J23
VSSIO_PCIECLK_1
VSSIO_PCIECLK_2
VSSIO_PCIECLK_3
VSSIO_PCIECLK_4
VSSIO_PCIECLK_5
VSSIO_PCIECLK_6
VSSIO_PCIECLK_7
VSSIO_PCIECLK_8
VSSIO_PCIECLK_9
VSSIO_PCIECLK_10
VSSIO_PCIECLK_11
VSSIO_PCIECLK_12
VSSIO_PCIECLK_13
USB PHY core power
+3V_SB_VDDPL_33_SYS
15mils
47mA System CLK Gen PLLs analog power
+1.1V_S5_SB_VDDPL_11_SYS_S
15mils
62mA System CLK Gen PLLs analog power
+3V_S5_SB_VDDXL_33_S
L20
15mils
C342
0.1U/10V_4
xx mA
C370
*0.1U/10V_4
2
SB820M
L33
VSSIO_USB_1
VSSIO_USB_2
VSSIO_USB_3
VSSIO_USB_4
VSSIO_USB_5
VSSIO_USB_6
VSSIO_USB_7
VSSIO_USB_8
VSSIO_USB_9
VSSIO_USB_10
VSSIO_USB_11
VSSIO_USB_12
VSSIO_USB_13
VSSIO_USB_14
VSSIO_USB_15
VSSIO_USB_16
VSSIO_USB_17
VSSIO_USB_18
VSSIO_USB_19
VSSIO_USB_20
VSSIO_USB_21
VSSIO_USB_22
VSSIO_USB_23
VSSIO_USB_24
VSSIO_USB_25
VSSIO_USB_26
VSSIO_USB_27
VSSIO_USB_28
1
+1.1V_S5_SB_VDDCR_11_S
1
113mA
2
VDDIO_AZ_S
VDDXL_33_S
Support S3 wake up
C384
2.2U/6.3V_6
2
VDDAN_11_USB_S_1
VDDAN_11_USB_S_2
F26
G26
+3V_S5_SB_VDDIO_33_S
C339
*0.1U/10V_4
15mils
CORE S5
C11
D11
20mils
VDDCR_11_S_1
VDDCR_11_S_2
32mA
Hardware monitor analog / I/O power
1.4A/220ohm_6
1
1
xx mA
USB PHY DLL analog power
+1.1VSUS
C373
1U/10V_4
VDDAN_33_USB_S_1
VDDAN_33_USB_S_2
VDDAN_33_USB_S_3
VDDAN_33_USB_S_4
VDDAN_33_USB_S_5
VDDAN_33_USB_S_6
VDDAN_33_USB_S_7
VDDAN_33_USB_S_8
VDDAN_33_USB_S_9
VDDAN_33_USB_S_10
VDDAN_33_USB_S_11
VDDAN_33_USB_S_12
A21
D21
B21
K10
L10
J9
T6
T8
+3V_S5
25-MHz XTAL I/O Power
WoL--> +3.3V_S5 rail
Non-WoL--> +3.3V_S0 rail
C358
2.2U/6.3V_6
2
B
C148
10U/6.3V_8
A18
A19
A20
B18
B19
B20
C18
C20
D18
D19
D20
E19
VDDIO_33_S_1
VDDIO_33_S_2
VDDIO_33_S_3
VDDIO_33_S_4
VDDIO_33_S_5
VDDIO_33_S_6
VDDIO_33_S_7
VDDIO_33_S_8
1
2
C149
10U/6.3V_8
2
1
Support S3 wake up
50mils
+3VSUS_SB_VDDAN_33_USB_S
2
1.4A/220ohm_6
20mils
C357
1U/10V_4
658mA
1
L12
VDDAN_11_SATA_1
VDDAN_11_SATA_4
VDDAN_11_SATA_2
VDDAN_11_SATA_3
VDDAN_11_SATA_5
VDDAN_11_SATA_6
VDDAN_11_SATA_7
1
C363
1U/10V_4
USB PHY analog / I/O Power
50mils
VDDPL_33_SATA
AJ20
AF18
AH20
AG19
AE18
AD18
AE16
2
1
C364
0.1U/10V_4
2
C365
0.1U/10V_4
2
C157
22U/6.3V_8
1
DC R=0.008Ω
+3VSUS
567mA
+1.1V_SB_VDDAN_11_SATA
AD14
3.3V_S5 I/O
+1.1V_SB_VDDAN_11_SATA
4A/42ohm_8
1
L13
2
SATA PHY analog / I/O Power
+1.1V
C349
*0.1U/10V_4
SERIAL ATA
C348
2.2U/6.3V_6
USB I/O
+3V_SB_VDDPL_33_SATA
S5 I/O Power
PLL
1.4A/220ohm_6
1
L35
15mils
2
+3V
93mA
SB800
VSSIO_SATA_1
VSSIO_SATA_2
VSSIO_SATA_3
VSSIO_SATA_4
VSSIO_SATA_5
VSSIO_SATA_6
VSSIO_SATA_7
VSSIO_SATA_8
VSSIO_SATA_9
VSSIO_SATA_10
VSSIO_SATA_11
VSSIO_SATA_12
VSSIO_SATA_13
VSSIO_SATA_14
VSSIO_SATA_15
VSSIO_SATA_16
VSSIO_SATA_17
VSSIO_SATA_18
VSSIO_SATA_19
GROUND
L42
C347
0.1U/10V_4
2
CLKGEN I/O
+3V
FLASH I/O
1.8V GPIOD I/O Power
+1.1V_SB_VDDCR
xx mA
VDDAN_11_CLK_1
VDDAN_11_CLK_2
VDDAN_11_CLK_3
VDDAN_11_CLK_4
VDDAN_11_CLK_5
VDDAN_11_CLK_6
VDDAN_11_CLK_7
VDDAN_11_CLK_8
Not used: Connected to GND through a 0Ω.
A-Link Express III/PCIe PLL power
N13
R15
N17
U13
U17
V12
V18
W 12
W 18
1
D
510mA
100mils
VDDCR_11_1
VDDCR_11_2
VDDCR_11_3
VDDCR_11_4
VDDCR_11_5
VDDCR_11_6
VDDCR_11_7
VDDCR_11_8
VDDCR_11_9
2
C382
0.1U/10V_4
Part 3 of 5
SB800
VDDIO_33_PCIGP_1
VDDIO_33_PCIGP_2
VDDIO_33_PCIGP_3
VDDIO_33_PCIGP_4
VDDIO_33_PCIGP_5
VDDIO_33_PCIGP_6
VDDIO_33_PCIGP_7
VDDIO_33_PCIGP_8
VDDIO_33_PCIGP_9
VDDIO_33_PCIGP_10
VDDIO_33_PCIGP_11
VDDIO_33_PCIGP_12
CORE S0
1
AH1
V6
Y19
AE5
AC21
AA2
AB4
AC8
AA7
AA9
AF7
AA19
2
1
C336
0.1U/10V_4
2
C334
0.1U/10V_4
2
C113
22U/6.3V_8
Core logic power
131mA
+3V_SB_VDDIO_33_PCIGP
1
*0/short_6
PCI/GPIO I/O
3.3V I/O power
R74
+3V
VSS_1
VSS_2
VSS_3
VSS_4
VSS_5
VSS_6
VSS_7
VSS_8
VSS_9
VSS_10
VSS_11
VSS_12
VSS_13
VSS_14
VSS_15
VSS_16
VSS_17
VSS_18
VSS_19
VSS_20
VSS_21
VSS_22
VSS_23
VSS_24
VSS_25
VSS_26
VSS_27
VSS_28
VSS_29
VSS_30
VSS_31
VSS_32
VSS_33
VSS_34
VSS_35
VSS_36
VSS_37
VSS_38
VSS_39
VSS_40
VSS_41
VSS_42
VSS_43
VSS_44
VSS_45
VSS_46
VSS_47
VSS_48
VSS_49
VSS_50
VSS_51
VSS_52
VSSPL_SYS
VSSIO_PCIECLK_14
VSSIO_PCIECLK_15
VSSIO_PCIECLK_16
VSSIO_PCIECLK_17
VSSIO_PCIECLK_18
VSSIO_PCIECLK_19
VSSIO_PCIECLK_20
VSSIO_PCIECLK_21
VSSIO_PCIECLK_22
VSSIO_PCIECLK_23
VSSIO_PCIECLK_24
VSSIO_PCIECLK_25
VSSIO_PCIECLK_26
VSSIO_PCIECLK_27
AJ2
A28
A2
E5
D23
E25
E6
F24
N15
R13
R17
T10
P10
V11
U15
M18
V19
M11
L12
L18
J7
P3
V4
AD6
AD4
AB7
AC9
V8
W9
W 10
AJ28
B29
U4
Y18
Y10
Y12
Y11
AA11
AA12
G4
J4
G8
G9
M12
AF25
H7
AH29
V10
P6
N4
L4
L8
D
C
M20
H23
H26
AA21
AA23
AB23
AD23
AA26
AC26
Y20
W 21
W 20
AE26
L21
K20
B
Part 5 of 5
+1.1VSUS_SB_VDDCR_11_USB_S
+3V
+3V_SB_VDDPL_33_SYS
1
C340
0.1U/10V_4
+1.1V_S5
C381
*0.1U/10V_4
+3V_S5
WoL--> +1.1V_S5 rail
Non-WoL--> +1.1V_S0 rail
As GPIOs: Stuff 0.1uF
Size
Date:
5
4
3
2
A
ai
tm
C331
*2.2U/6.3V_6
f@
C375
0.1U/10V_4
ho
1
C333
0.1U/10V_4
C153
2.2U/6.3V_6
in
<20100310(C3A)_Follow CRB>
Connect +3VSUS_SB_VDDPL_33_USB_S to
+3VSUS directly.
C400
2.2U/6.3V_6
*0/short_6
Quanta Computer Inc.
PROJECT : ZH9
Document Number
xa
R287
*0/short_6
he
2
2
C385
*0.1U/10V_4
R117
1
1.4A/220ohm_6
1
L43
+3V_S5_SB_VDDAN_33_HWM_S
+3VSUS_SB_VDDPL_33_USB_S
Support S3 wake up
1
+3VSUS
2
+1.1V_S5_SB_VDDPL_11_SYS_S
A
C376
2.2U/6.3V_6
l.c
om
C341
0.1U/10V_4
1.4A/220ohm_6
2
C144
10U/6.3V_8
1
1
L36
2
C335
2.2U/6.3V_6
2
2
*0/short_6
2
R111
1
+3V_S5
*0/short_6
1
R305
1
Support S3 wake up
2
+1.1VSUS
2
+3V_S5_SB_VDDIO_AZ_S
SB820M
Rev
4A
SB820-PWR/DECOUPLING 4/5
Sheet
Sunday, March 28, 2010
1
13
of
40
5
4
3
2
1
STANDARD STRAPS
<20091202(A1A)_Confirm with AMD's Horace>
PCI_CLK4 PU with 10K for both internal and external CLK Gen.
D
+3V_S5
+3V
+3V
R61
*10K/J_4
+3V
+3V_S5
R82
*10K/J_4
R66
*10K/J_4
R79
10K/J_4
R81
10K/J_4
R67
10K/J_4
R80
*10K/J_4
D
+3V_S5
R146
ICK@10K/J_4
R132
10K/J_4
<11> EC_PWM2
<11> EC_PWM3
<10> LPC_CLK1
<10> LPC_CLK0
<10> PCI_CLK4
<10> PCI_CLK3
<10> PCI_CLK2
<10> PCI_CLK1
<11> ACZ_SDOUT
R60
10K/J_4
R68
*10K/J_4
R343
10K/J_4
R138
*10K/J_4
R119
2.2K/J_4
R130
*2.2K/J_4
AZ_SDOUT
PCI_CLK1
PCI_CLK2
PCI_CLK3
PCI_CLK4
LPC_CLK0
LPC_CLK1
EC_PWM3 EC_PWM2
LOW POWER
MODE
PCIe Gen II
Watchdog
Timer Enable
USE
DEBUG
STRAPS
non_Fusion
CLK MODE
EC
ENABLED
CLKGEN
ENABLED
H, H=Reserved
C
C
PULL
HIGH
ICK@DEFAULT
PULL
LOW
PERFORMANCE PCIe Gen I
MODE
Watchdog
Timer Disable
DEFAULT
DEFAULT
This is
required as
the low
power mode
is not
supported on
the SB8xx.
B
IGNORE
DEBUG
STRAPS
ICK@DEFAULT
FUSION
CLK MODE
DEFAULT
Not Applicable to
SB820M--Leave
provision for PD.
H, L=SPI ROM
EC
DISABLED
CLKGEN
DISABLED
DEFAULT
ECK@DEFAULT
L, H=LPC ROM DEFAULT
L, L=Reserved
PCICLK4:
CPU/NB HT Clock Selection
This strap is not used if the strap CLKGEN is
configured for external clock generator mode.
internal have
pull Hi 10K
DEBUG STRAPS
B
SB800 HAS 15K INTERNAL PU FOR PCI_AD[27:23]
PULL
LOW
1
R112
*2.2K/J_4
2
R299
*2.2K/J_4
2
2
R306
*2.2K/J_4
2
PULL
HIGH
A
R291
*2.2K/J_4
2
R292
*2.2K/J_4
1
1
1
AD23
AD24
AD25
AD26
AD27
1
<10>
<10>
<10>
<10>
<10>
PCI_AD27
PCI_AD26
PCI_AD25
PCI_AD24
PCI_AD23
USE PCI
PLL
DISABLE ILA
AUTORUN
USE FC
PLL
USE DEFAULT
PCIE STRAPS
DISABLE PCI
MEM BOOT
DEFAULT
DEFAULT
DEFAULT
DEFAULT
DEFAULT
BYPASS
PCI PLL
ENABLE ILA
AUTORUN
BYPASS FC
PLL
USE EEPROM
PCIE STRAPS
ENABLE PCI
MEM BOOT
A
Quanta Computer Inc.
PROJECT : ZH9
Size
Document Number
Rev
4A
SB820-STRAPS,PWRGD 5/5
Date:
5
4
3
Sunday, March 28, 2010
2
Sheet
14
1
of
40
5
4
3
Standard
Connector
75
76
81
82
87
88
93
94
99
100
105
106
111
112
117
118
123
124
4
6
7
8
9
10
2
22
24
26
28
29
33
35
37
39
41
43
47
49
51
53
55
57
59
61
63
65
67
69
71
73
32
34
36
38
40
42
44
46
48
50
52
54
56
58
60
62
64
66
68
70
72
74
75
76
77
78
79
80
81
82
84
83
85
86
87
88
89
90
91
92
93
94
95
96
97
98
99
100
101
103
102
104
105
106
107
108
109
110
111
112
113
114
115
116
117
118
120
119
121
122
123
124
125
126
127
128
129
130
131
132
133
134
135
136
137
139
138
140
141
142
143
144
145
146
147
<3> M_A_BANK[0..2]
148
149
150
151
152
153
154
155
157
M_A_BANK0
M_A_BANK1
M_A_BANK2
109
108
79
BA0/BA1
BA1/BA0
BA2
M_A_DM0
M_A_DM1
M_A_DM2
M_A_DM3
M_A_DM4
M_A_DM5
M_A_DM6
M_A_DM7
11
28
46
63
136
153
170
187
DM0
DM1
DM2
DM3
DM4
DM5
DM6
DM7
156
158
159
160
161
162
163
164
165
200
166
199
167
168
169
170
171
172
173
175
174
176
177
178
179
180
181
182
183
184
185
186
187
188
189
<3> M_A_DM[0..7]
190
191
192
194
193
195
196
197
198
199
SMbus address A0
R258
*0/short_4
R263
*0/short_4
+SMDDR_VREF
R154
*1K/F_4
R149
*0/short_6
<3>
<3>
<3>
<3>
<3>
<3>
<3>
<3>
M_A_DQSP0
M_A_DQSP1
M_A_DQSP2
M_A_DQSP3
M_A_DQSP4
M_A_DQSP5
M_A_DQSP6
M_A_DQSP7
12
29
47
64
137
154
171
188
DQS0
DQS1
DQS2
DQS3
DQS4
DQS5
DQS6
DQS7
<3>
<3>
<3>
<3>
<3>
<3>
<3>
<3>
M_A_DQSN0
M_A_DQSN1
M_A_DQSN2
M_A_DQSN3
M_A_DQSN4
M_A_DQSN5
M_A_DQSN6
M_A_DQSN7
10
27
45
62
135
152
169
186
DQS0#
DQS1#
DQS2#
DQS3#
DQS4#
DQS5#
DQS6#
DQS7#
<3>
<3>
<3>
<3>
M_A_CLKP1
M_A_CLKN1
M_A_CLKP2
M_A_CLKN2
101
103
102
104
73
74
<3> M_A_CKE0
<3> M_A_CKE1
MEM_VREF
R151
*1K/F_4
C201
0.01U/25V_4
<3>
<3>
<3>
<3>
<3>
C202
1000P/50V_4
110
115
113
114
121
M_A_RAS#
M_A_CAS#
M_A_WE#
M_A_CS#0
M_A_CS#1
116
120
<3> M_A_ODT0
<3> M_A_ODT1
B
SA0_A
SA1_A
200
202
<11,23> SB_SDATA0
<11,23> SB_SCLK0
199
+3V
+1.5VSUS
+SMDDR_VREF
R62
*1K/F_4
<3>
R57
*0/short_6
C50
1U/6.3V_4
30
M_A_RST#
<20100115(B2A)>
Add Power Symbol for +SMDDR_VTERM
disconnect issue.
<3> MEMHOT_MA#
+SMDDR_VTERM
MEMHOT_MA#
MEM_VREF
MEM_VREFCA
C32
+1.5VSUS
+SMDDR_VTERM
*0.1U/10V_4
MEM_VREFCA
C35
4.7U/6.3V_6
R58
*1K/F_4
C90
0.01U/25V_4
197
201
C38
C31
0.22U/6.3V_4 0.22U/6.3V_4
C91
1000P/50V_4
1
126
203
204
2
3
8
9
13
14
19
20
25
26
31
32
CKE0
CKE1
RAS#
CAS#
WE#
S0#
S1#
ODT0
ODT1
SA0
SA1
NC1
NC2
TEST
77
122
125
M_A_TEST
VSS51
VSS50
VSS49
VSS48
VSS47
VSS46
VSS45
VSS44
VSS43
VSS42
VSS41
VSS40
VSS39
VSS38
VSS37
VSS36
VSS35
VSS34
VSS33
VSS32
VSS31
VSS30
VSS29
VSS28
VSS27
196
195
190
189
185
184
179
178
173
172
168
167
162
161
156
155
151
150
145
144
139
138
134
133
128
C82
100U/6.3V_3528
D
C143
100U/6.3V_3528
+1.5VSUS
C132
0.1U/10V_4
C107
*0.1U/10V_4
C117
0.1U/10V_4
C95
*0.1U/10V_4
Confirmed with AMD FAE Reden
MA_EVENT_L should be PU(R8004) with 2.2K, not 1K
Not installed by default
C127
*0.1U/10V_4
R43
*2.2K/J_4
+1.5VSUS
R33
*2.2K/J_4
2
1
C126
*0.1U/10V_4
C138
0.1U/10V_4
C94
*0.1U/10V_4
B
SDA
SCL
VDDspd
RST#
EVENT#
VREF
VrefCA
VTT1
VTT2
VSS0
VSS1
VSS2
VSS3
VSS4
VSS5
VSS6
VSS7
VSS8
VSS9
VSS10
VSS11
+SMDDR_VTERM <30>
+SMDDR_VREF <30>
Size
CPU_MEMHOT# <10,11>
Date:
4
C104
*0.1U/10V_4
C139
0.1U/10V_4
T61
H=4
Q4
*MMBT3904
3
C131
0.1U/10V_4
C
DDR3_SO-DIMM_SOCKET_1.5V_Standard
+1.5VSUS
MEMHOT_MA#
5
C119
0.1U/10V_4
37
38
43
44
48
49
54
55
60
61
65
66
71
72
127
A
198
CK0
CK0#
CK1
CK1#
+1.5VSUS
ho
+1.5VSUS
SA0_A
SA1_A
M_A_DQ0
M_A_DQ1
M_A_DQ2
M_A_DQ3
M_A_DQ4
M_A_DQ5
M_A_DQ6
M_A_DQ7
M_A_DQ8
M_A_DQ9
M_A_DQ10
M_A_DQ11
M_A_DQ12
M_A_DQ13
M_A_DQ14
M_A_DQ15
M_A_DQ16
M_A_DQ17
M_A_DQ18
M_A_DQ19
M_A_DQ20
M_A_DQ21
M_A_DQ22
M_A_DQ23
M_A_DQ24
M_A_DQ25
M_A_DQ26
M_A_DQ27
M_A_DQ28
M_A_DQ29
M_A_DQ30
M_A_DQ31
M_A_DQ36
M_A_DQ37
M_A_DQ35
M_A_DQ39
M_A_DQ38
M_A_DQ32
M_A_DQ33
M_A_DQ34
M_A_DQ40
M_A_DQ41
M_A_DQ46
M_A_DQ47
M_A_DQ44
M_A_DQ45
M_A_DQ42
M_A_DQ43
M_A_DQ52
M_A_DQ49
M_A_DQ54
M_A_DQ55
M_A_DQ53
M_A_DQ48
M_A_DQ51
M_A_DQ50
M_A_DQ61
M_A_DQ60
M_A_DQ63
M_A_DQ62
M_A_DQ56
M_A_DQ57
M_A_DQ58
M_A_DQ59
f@
C
*4.7K/J_4
*4.7K/J_4
VSS12
VSS13
VSS14
VSS15
VSS16
VSS17
VSS18
VSS19
VSS20
VSS21
VSS22
VSS23
VSS24
VSS25
VSS26
R262
R260
DDR3 SO-DIMM
(Standard )
200
+3V
5
7
15
17
4
6
16
18
21
23
33
35
22
24
34
36
39
41
51
53
40
42
50
52
57
59
67
69
56
58
68
70
129
131
141
143
130
132
140
142
147
149
157
159
146
148
158
160
163
165
175
177
164
166
174
176
181
183
191
193
180
182
192
194
+
45
D
CON_SODIMM200_STD_V1
30
31
M_A_DQ[0..63] <3>
CN15
DQ0
DQ1
DQ2
DQ3
DQ4
DQ5
DQ6
DQ7
DQ8
DQ9
DQ10
DQ11
DQ12
DQ13
DQ14
DQ15
DQ16
DQ17
DQ18
DQ19
DQ20
DQ21
DQ22
DQ23
DQ24
DQ25
DQ26
DQ27
DQ28
DQ29
DQ30
DQ31
DQ32
DQ33
DQ34
DQ35
DQ36
DQ37
DQ38
DQ39
DQ40
DQ41
DQ42
DQ43
DQ44
DQ45
DQ46
DQ47
DQ48
DQ49
DQ50
DQ51
DQ52
DQ53
DQ54
DQ55
DQ56
DQ57
DQ58
DQ59
DQ60
DQ61
DQ62
DQ63
3
A
ai
20
23
25
A0
A1
A2
A3/A4
A4/A3
A5/A6
A6/A5
A7/A8
A8/A7
A9
A10/AP
A11
A12_BC#
A13
A14
A15/BA3
tm
19
21
27
98
97
96
95
92
91
90
86
89
85
107
84
83
119
80
78
2
in
18
Quanta Computer Inc.
PROJECT : ZH9
Document Number
xa
16
he
12
14
l.c
om
2
3
5
+
M_A_A0
M_A_A1
M_A_A2
M_A_A3
M_A_A4
M_A_A5
M_A_A6
M_A_A7
M_A_A8
M_A_A9
M_A_A10
M_A_A11
M_A_A12
M_A_A13
M_A_A14
M_A_A15
1
11
13
VDD0
VDD1
VDD2
VDD3
VDD4
VDD5
VDD6
VDD7
VDD8
VDD9
VDD10
VDD11
VDD12
VDD13
VDD14
VDD15
VDD16
VDD17
1
15
1
+1.5VSUS
<3> M_A_A[0..15]
17
2
Rev
4A
DDR3 SODIMM: ONE CHANNEL
Sheet
Sunday, March 28, 2010
1
15
of
40
4
Hall IC
APX9132H
AI-TRG
R254
+3VPCU
ESD
TYPE
PU
2KV
CMOS
N/A
3
1
LID#
+3V
CCD_POWER
*5.5V/25V/410P_4
2
1
LCDVCC
N/A
<20100125(B2A)>
Change Hall IC from AL003661003
to AL009132001 ; non-stuff R254
C314
LCDVCC_1
0.1U/10V_4
3
CMOS
2
+3V
MR1
APX9132H
D
R38
1
CAMERA POWER(CCD)
LCD POWER SWITCH(LDS)
D28
EM-6781-T3 1.5KV
2
*100K/J_4
R255
Irush=1.5A
*0/short_6
<20100309a(C3A)>
Reserve R375, for S3 hang up issue
*0/short_8
C309
<20100319a(RAMP)>
Delete R375 (no need)
C55
C70
C56
C57
C58
0.1U/10V_4
2.2U/6.3V_6
0.1U/10V_4
0.01U/16V_4
2.2U/6.3V_6
0.15A
CCD_POWER
10U/10V_8
+
5
HALL IC(HSR)
C311
1000P/50V_4
C310
*0.1U/10V_4
D
R256
10K/J_4
D27
BAS316
LID#
LCD MODULE(LDS)
<25>
+3V
+3V
VIN
3
DISPON
R253
10K/J_4
2
6
OUT
1
IN
GND
2
3
ON/OFF
GND
5
3
4
1
2
INT_LVDS_BLON
Q14
IC(5P) G5243AT11U
<8>
Confirmed with AMD Horace
R257
4.7K/J_4 LVDS_DIGON/ LVDS_BLON/ LVDS_ENA_BL need to be
pulled down with 4.7K
1
2N7002K
R49
4.7K/J_4
3
Confirmed with AMD Horace
LVDS_DIGON/ LVDS_BLON/ LVDS_ENA_BL need to be
pulled down with 4.7K
C
1
2
EC_FPBACK# <25>
Q16
DTC144EU
<20100115(B2A)>
Add F1(fuse) to meet IEC 60950-1
2nd certificationand.
C2
0.1U/10V_4
F1
2
+5V
+5V_CRT
1
D25
SSM14
CRTVDD5
SMD1206P100TF/1A/1.8A/6V
<Layout note>
PLACE inductances 90 DEGREE FROM EACH OTHER
B
<8>
CRT_G
<8>
CRT_B
<20090810(A1A)_46659_RS880_Errata_nda_1.10>
The R channel's term. R change 140ohm (For the
voltage level mismatch, the Red is higher)
R244
R245
R243
C306
10P/50V_4
10P/50V_4
16
L31
3A/47ohm_6
CRT_R1
L32
3A/47ohm_6
CRT_G1
L30
3A/47ohm_6
CRT_B1
C307
C304
10P/50V_4
C303
10P/50V_4
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
25
26
27
28
29
30
C
31
32
31
32
C305
10P/50V_4
<20091215(A1A)_Follow EMI's Suggest>
Change series component of DMIC_DAT from 33ohm to bead
Change series component of DMIC_CLK from 0ohm to bead
CN11
6
1
7
2
8
3
9
4
10
5
<EMI>
T1
1A/470ohm_6
L5
<19> DMIC_DAT
DMIC_DAT_CN
11
CRT_11
12
CRT_SDA
13
CRTHSYNC
C52
C53
14
CRTVSYNC
*68P/50V_4
*68P/50V_4
15
CRT_SCL
L4
<19> DMIC_CLK
1A/470ohm_6
DMIC_CLK_CN
B
10P/50V_4
17
140/F_4 150/F_4 150/F_4
C308
CN1
LCD CONN
<20100128(B2A)>
Change L30,L31,L32 from CX8LL680001 to CX08T470004
CRT_R
C39
0.1U/50V_6
1
2
LCDVCC
3
LCDVCC
4
LCDVCC
5
+3V
CCD_POWER
6
CCD_POWER
DMIC_DAT_CN
7
DMIC_CLK_CN
8
C27
*0.1U/10V_4
9
10
<11>
USBP311
<11>
USBP3+
C20
*0.1U/10V_4
12
DISPON
13
<20091202(A1A)_45485_sb800_scl_nda_1.04>
LCD_VADJ
14
Reserve 0.1uF for USB P/N if trace <=10"
15
TXLOUT216
<8>
TXLOUT2TXLOUT2+
17
<8>
TXLOUT2+
18
TXLOUT119
<8>
TXLOUT1TXLOUT1+
20
<8>
TXLOUT1+
21
TXLOUT022
<8>
TXLOUT0TXLOUT0+
23
<8>
TXLOUT0+
24
TXLCLKOUT25
<8> TXLCLKOUTTXLCLKOUT+
26
<8> TXLCLKOUT+
27
LCD_CLK
28
<8>
LCD_CLK
LCD_DATA
29
<8>
LCD_DATA
30
+3V
<20100128(B2A)>
Change CN11(CRT CONN) from DFDS15FR138 to
DFDS15FR204.
<8>
V_BLIGHT
C49
4.7U/25V_8
IN
BL#
<8> INT_LVDS_DIGON
CRT(CRT)
*0/short_6
U2
C74
4.7U/10V_6
Q15
2N7002K
20mA*24pcs=480mA
R32
CRT CONN
+3V
R259
4.7K/J_4 LCD_CLK
R261
4.7K/J_4 LCD_DATA
<EMI>
C313
C312
*220P/50V_4
*220P/50V_4
<Layout note>
Close to CONN
U10
CRTVDD5
C301
A
0.22U/25V_6
CRT_BYP
1
VCC_SYNC SYNC_OUT2
SYNC_OUT1
VCC_DDC
BYP
SYNC_IN2
VCC_VIDEO
SYNC_IN1
16
14
3
4
5
VIDEO_1
VIDEO_2
VIDEO_3
DDC_IN1
DDC_IN2
10
11
6
GND
DDC_OUT1
DDC_OUT2
9
12
7
8
2
+3V
C5
0.1U/10V_4
CRT_R1
CRT_G1
CRT_B1
CRT_VSYNC1
CRT_HSYNC1
R240
R241
18/J_4 VSYNC_R
18/J_4 HSYNC_R
L28
L29
CRTVSYNC
CRTHSYNC
0.5A/22ohm_6
0.5A/22ohm_6
<8> INT_LVDS_PWM
<25> CONTRAST
15
13
CRT_VSYNC
CRT_HSYNC
CRTVDD5
<8>
<8>
R242
4.7K/J_4
CRT_SCL
CRT_SDA
R3
4.7K/J_4
CRT_SCL <8>
CRT_SDA <8>
C4
*10P/50V_4
CRTVDD5
C300
*100P/50V_4
CRTVSYNC
C302
*100P/50V_4
CRTHSYNC
C1
*100P/50V_4
CRT_SCL
C3
*100P/50V_4
CRT_SDA
R40
*0/short_4
R37
*0/J_4
C51
*0.1U/10V_4
A
Quanta Computer Inc.
<20090812(A1A)_46105_rs880_scl_nda_1.03>
CRT DDC are +5V tolerance
IP4772_Rout=10ohm
LCD_VADJ
PROJECT : ZH9
Size
Document Number
Rev
4A
CRT/LVDS
Date:
5
4
3
2
Sunday, March 28, 2010
Sheet
1
16
of
40
5
4
3
2
1
HDMI HPD SENSE
(HDM)
+3V
Close to HDMI Connector
Q3
HDM@2N7002K
HDM@715/F_4
TX2_HDMI+
R24
HDM@715/F_4
TX2_HDMI-
R23
HDM@715/F_4
TX1_HDMI+
R21
HDM@715/F_4
TX1_HDMI-
R20
HDM@715/F_4
TX0_HDMI+
R16
HDM@715/F_4
TX0_HDMI-
R247
HDM@10K/F_4
D
+3V
1
2
R28
3
+5V
3
D
R27
Q1
R10
HDMI_DET_R
2
HDMI_DET
R249
R251
HDM@715/F_4
TXC_HDMI+
R248
HDM@715/F_4
TXC_HDMI-
HDM@200K/F_4
R252
HDM@0_4
3
<8> INT_HDMI_HPD
HDM@2N7002K
1
HDM@10K/F_4
HDM@100K/F_4
R9
HDM@200K/F_4
R246
2
HDM@0_4
HDMI_HPD_EC# <25>
Q2
HDM@2N7002K
ESD Protect
1
EMI reserve for HDMI(HDM)
C
C
HDMI PORT
close to HDMI connector
Close connector
CN12
U11
TX2_HDMI+
HDMI_DDC_CLK
HDMI_DDC_DATA
R26
*HDM@100/F_4
TX2_HDMI-
HDMI_DET
1
2
3
4
5
TX1_HDMI+
1
2
GND_3/8
4
5
10
9
10
9
7
6
7
6
HDMI_DDC_CLK
HDMI_DDC_DATA
<7> TX2_HDMI+
R22
*HDM@100/F_4
TX0_HDMI+
U12
TX0_HDMI+
TX0_HDMITXC_HDMI+
TXC_HDMI-
1
2
3
4
5
R19
*HDM@100/F_4
1
2
GND_3/8
4
5
10
9
10
9
TX0_HDMI+
TX0_HDMI-
7
6
7
6
TXC_HDMI+
TXC_HDMI-
TXC_HDMI-_R
U14
TX2_HDMI+
TX2_HDMIR250
*HDM@100/F_4
TXC_HDMI-
TX1_HDMI+
TX1_HDMI-
1
2
3
4
5
1
2
GND_3/8
4
5
10
9
10
9
TX2_HDMI+
TX2_HDMI-
7
6
7
6
TX1_HDMI+
TX1_HDMI-
2
+5V
HDMI_DDC_CLK
HDMI_DDC_DATA
<8> HDMI_DDC_CLK
<8> HDMI_DDC_DATA
*HDM@RClamp0524P
F2
TXC_HDMI+
TX0_HDMITXC_HDMI+_R
<7> TX0_HDMI-
<20100115(B2A)>
Add F2(fuse) to meet IEC 60950-1
2nd certificationand.
TX0_HDMI-
B
TX1_HDMITX0_HDMI+
<7> TX1_HDMI<7> TX0_HDMI+
+5V_HDMI
1
SHELL1
D2+SHELL3
D2 Shield
D2D1+
D1 Shield
D1D0+
D0 Shield
D0CK+
CK Shield
CKCE Remote
NC
DDC CLK
DDC DATA
GND
+5V
HP DET
SHELL4
SHELL2
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
TX2_HDMITX1_HDMI+
<7> TX2_HDMI<7> TX1_HDMI+
HDMI_DET
*HDM@RClamp0524P
TX1_HDMI-
TX2_HDMI+
HDM@SMD1206P100TF/1A/1.8A/6V
HDMI_DET
<20100310(C3A)>
Delete D26(BC0SSM14Z21),
for HDMI certification
20
22
B
23
21
HDM@QJ1119C-NK01-8F
C6
*HDM@RClamp0524P
[email protected]/6.3V_4
<Layout note>
colse to HDMI connector
R14
+5V
*HDM@0/short_4
HDMI_DDC_CLK
HDMI_DDC_DATA
TXC_HDMI+_R
TXC_HDMI-_R
<7> TXC_HDMI+
<7> TXC_HDMIR13
R12
R11
[email protected]/J_4
[email protected]/J_4
*HDM@0/short_4
A
A
<20091215(A1A)_Follow EMI's suggestion>
add a common mode chock in HDMI CLK to
prevent AMD issue
Quanta Computer Inc.
<20100324(RAMP)>
Delete L1 and change R13,R14 to shortpad.
l.c
om
PROJECT : ZH9
Size
Document Number
Date:
Sunday, March 28, 2010
f@
ho
tm
2
in
3
xa
4
he
5
ai
HDMI
Rev
4A
Sheet
1
17
of
40
5
4
3
<20100303(C3A)>
Change CP1~CP6 footprint from 8p4r-0402 to
8p4r-0402-smt, for SMT open issue.
KEYBOARD(KBC)
2
1
BT
BLUETOOTH(BTM)
<EMI>
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
D
MX7
MX6
MX5
MY0
MY1
MY2
MX4
MY3
MY4
MY5
MY6
MY7
MY8
MX3
MY9
MX2
MX1
MY10
MY11
MX0
MY12
MY13
MY14
MY15
MX7
MX6
MX5
MY0
MY1
MY2
MX4
MY3
MY4
MY5
MY6
MY7
MY8
MX3
MY9
MX2
MX1
MY10
MY11
MX0
MY12
MY13
MY14
MY15
MX7
MX6
MX5
MY0
MY1
MY2
MX4
MY3
MY4
MY5
MY6
MY7
MY8
MX3
MY9
MX2
MX1
MY10
MY11
MX0
MY12
MY13
MY14
MY15
<25>
<25>
<25>
<25>
<25>
<25>
<25>
<25>
<25>
<25>
<25>
<25>
<25>
<25>
<25>
<25>
<25>
<25>
<25>
<25>
<25>
<25>
<25>
<25>
7
5
3
1
7
5
3
1
7
5
3
1
7
5
3
1
7
5
3
1
7
5
3
1
8
6
4
2
8
6
4
2
8
6
4
2
8
6
4
2
8
6
4
2
8
6
4
2
+3V
+3V
D
CP3
*220P_8P4R
Q13
CP4
*220P_8P4R
CN7
61mA
1
+3V
3
BT_POWER
C267
CP5
*220P_8P4R
*[email protected]/10V_4
<11>
<11>
BT@AO3413
+ C260
C258
[email protected]/25V_6 BT@1000P/50V_4
CP6
*220P_8P4R
1
2
3
4
5
USBP5+
USBP5C256
*[email protected]/10V_4
C257
7
6
BT@BT_CONN
*[email protected]/10V_4
R207
CP1
*220P_8P4R
<25> BT_POWERON#
<20091202(A1A)_45485_sb800_scl_nda_1.04>
Reserve 0.1uF for USB P/N if trace <=10"
BT@10K/J_4
C261
0402 size
[email protected]/10V_4
25
C
T77H056.00
T60H928.33
LED
CP2
*220P_8P4R
2
CN3
PWR
C
26
KB CONN
TOUCH PAD(TPD)
+5V
3mA
+5V_TP
<EMI>
L9
+5V
CN2
3A/120ohm_8
CX121T30001:3A/120ohm_8
B
7
8
C136
0.1U/10V_4
TP_L#
1
2
3
4
5
6
TP_R#
R101
4.7K/J_4
4.7K/J_4
<EMI>
+5V_TP
TPDATA_CN
TPCLK_CN
L8
L7
0.4A/120ohm_6
0.4A/120ohm_6
TPDATA
TPCLK
B
<25>
<25>
CX08T121000:0.4A/120ohm_6
CX121T04000:0.4A/120ohm_6
TP_CONN
<20100126(B2A)>
Change L9 from CS00004JA40 to CX121T30001 and L7,L8
from CS00003J951 to CX08T121000, for RF issue.
R104
C135
10P/50V_4
C134
10P/50V_4
<20100126(B2A)>
Change SW2,SW3 from DHP00AC1G00 to DHP00533K00, for SMT issue.
TP switch
D23
*14V/38V/100P_4
2
A
3
4
5
6
SW2
1
2
TP_R#
1
TP_L#
TP switch
D24
*14V/38V/100P_4
A
2
SW3
1
2
1
3
4
5
6
Quanta Computer Inc.
PROJECT : ZH9
Size
Document Number
Rev
4A
KB/BT/TP/LED/Power Connector
Date:
5
4
3
2
Sunday, March 28, 2010
Sheet
1
18
of
40
5
4
3
2
1
<Layout note>
AUDIO CODEC
LDO_OUT_3.3V
FILT_1.65V
D
+3V
+3V_ADO
R181
LDO_OUT_3.3V
AVDD_3.3 pin is output of
internal LDO. Do NOT connect
to external supply.
50mA
C241
1u/6.3V_4
C240
0.1u/10V_4
D
C254
C248
10U/10V_8 0.1u/10V_4
+3V_ADO
*0/short_6
ADOGND
ADOGND
C230
10U/10V_8
C276
0.1u/10V_4
C259
0.1u/10V_4
+5V
1.03A ; peak:2.5A
+3V_ADO
+5V_ADO
R233
*0/short_8
C284
C278
10U/10V_8 0.1u/10V_4
C234
1u/6.3V_4
+3V_ADO
C253
0.1u/10V_4
Note:
R226
To support Wake-on-Jack, the CODEC VAUX_3.3 pins
must be powered by a Standby supply.
0.1/F_1206
C235
10U/10V_8
C238
0.1u/10V_4
Place bypass caps very close to device.
10K only needed if supply to VAUX_3.3 is
removed during system re-start.
<20100126(B2A)>
Change R234,R239 from 0ohm(CS00003J951) to 6.8ohm(CS-6803J900), for SPL
Speaker (AMP)
Layout Note: Path from +5V to LPWR_5.0 and
RPWR_5.0 must be very low resistance ( <0.01 ohms).
<20100323(RAMP)>
Change R234,R239 from 6.8ohm(CS-6803J900) to 6.8ohm(CS-6802FB00), for cost and shortage issue.
SPK_R-
R234
6.8/F_4
SPK_R-_CN
C291
*47P/50V_4
CLASSD_5V
C294
FILT_1.8V
R189
C246
10U/10V_8
C275
0.1u/10V_4
C243
0.1u/10V_4
*1U/6.3V_4
C271
0.1u/10V_4
C269
0.1u/10V_4
C279
10U/10V_8
C281
10U/10V_8
ACZ_SDIN0_CODEC
C247
5
8
6
4
+3V_ADO
R216
SB_BEEP
33/J_4
C268
0.1u/10V_4
EAPD#
SPK_MUTE#
10
38
37
PC_BEEP
C_BIAS
PORTC_R
PORTC_L
SPDIF
GPIO0/EAPD#
GPIO1/SPK_MUTE#
100/J_4
4
35
26
1
Sense resistor 5.11K must be connected to
same power supply that is used for
VAUX_3.3 pins.
SENSE PIN A
C
SPEAKER-CON
C297
*47P/50V_4
C298
C299
*47P/50V_4
SPK_L+_CN
SENSE_A
36
R174
5.11K/F_4
DMIC_CLK_CH
40
1
SPK_L+
R239
6.8/F_4
PORTA_R
PORTA_L
39.2K/F_4
LINEOUT_JD#
R178
10K/F_4
MIC1_JD#
Earphone(AMP)
MIC_BIAS
MIC1_R1
MIC1_L1
32
31
30
<Layout note>20091223
follow EMI suggestion , modify PIN6 from dummy to ADOGND
<20100309(C3A)>
Change L22,L25 from 0ohm to CX08T601000, C272,C283 to CH1686K9B00, for EMI issue.
Port
Port
Port
Port
Port
Port
Port
25
24
HPOUT-R
HPOUT-L
23
22
21
20
19
EP_GND
RIGHT+
RIGHT-
AVEE
FLY_N
FLY_P
LEFT-
R182
SENSE_A
CN8
Port Configuration
DMIC_CLK
DMIC_1/2
LEFT+
35
34
33
CX20672-11Z
NC_DR
NC_DL
R185
CN9
*22p/50V_4
39
<16> DMIC_CLK
<16> DMIC_DAT
R237
R238
*1U/6.3V_4
SENSE_A
PORTB_R
PORTB_L
B_BIAS
<11>
SPK_R+
SPK_L-
17
CLASSDREF
12
15
27
28
29
2
7
18
26
BIT_CLK
SYNC
SDATA_IN
SDATA_OUT
JACK DETECT RESISTORS
AVEE
FLY_N
FLY_P
C270
1u/6.3V_4
C287
0.1u/10V_4
A:
B:
C:
D:
G:
J:
H:
Headphone jack (jack shared with S/PDIF)
Internal analog mono mic (stereo option)/Line In
Microphone jack
LineOut jack(need cap) or Headphone jack(cap less)
Internal stereo speakers
Optional Internal stereo digital mic
S/PDIF (jack shared with headphone)
HPOUT-L
R223
39/J_4
HPL
L22
1A/600ohm_6
HPL_SYS
HPOUT-R
R227
39/J_4
HPR
L25
1A/600ohm_6
HPR_SYS
<20100309(C3A)>
Change R223,R227 from 5.1ohm(CS-5102JB03)
to 39ohm(CS03902JB21), for FSOV spec
R230
R217
*1K/J_4
*1K/J_4
C283
C272
680P/50V_4
5
BLACK
D22
*14V/38V/100P_4
Normal Open Jack
C289
10U/10V_8
ADOGND
ADOGND
B
41
16
14
13
7
8
LINEOUT_JD#
680P/50V_4
B
11
1
2
6
3
4
1
33/J_4
RESET#
LPWR_5.0
*22p/50V_4
*0/short_4 ACZ_BCLK_CODEC
R204
9
RPWR_5.0
C252
R206
<11> ACZ_BITCLK_AUDIO
<11> ACZ_SYNC_AUDIO
<11> ACZ_SDIN0
<11> ACZ_SDOUT_AUDIO
*22p/50V_4
AVDD_5V
Use as needed for EMI.C265
FILT_1.65
2
5.5V/25V/410P_4
AVDD_3.3
1
<11> ACZ_RST#_AUDIO
FILT_1.8
U8
VAUX_3.3
VDD_IO
DVDD_3.3
AVDD_HP
D38
C
3
<20100119(B2A)_For ESDissue>
Add D38 for ESD issue
C295
*47P/50V_4
*0/short_6 SPK_R+_CN
*0/short_6 SPK_L-_CN
2
10K_4
<20100119(B2A)_FAE Request>
Change Pin41 from GND to AGND for thermal holes.
MIC_BIAS
System MIC(AMP)
ADOGND
Recommended EMI components
D12
*BAS316
D18
EAPD#
*BAS316
D11
AMP_MUTE#
R167
*0/short_4
R176
2.2K/J_4
<Layout note>
Place EMI components close to audio codec.
ACZ_RST#_AUDIO
SPK_R+_CH
L27
3A/120ohm_8
DCR:0.04ohm
SPK_R+
SPK_R-_CH
L26
3A/120ohm_8
DCR:0.04ohm
SPK_RR172
R183
R385
AMP_MUTE# <25>
SPK_L-_CH
L24
3A/120ohm_8
DCR:0.04ohm
SPK_L-
R415
R416
*0/short_4
*0/short_4
3A/120ohm_8
DCR:0.04ohm
SPK_L+
R417
R418
R419
R420
*0/short_4
*0/short_4
*0/short_4
*0/short_4
C286
C288
1000P/50V_4 1000P/50V_4
C229
2.2U/6.3V_6
MIC1_L2
R180
100/J_4
MIC1_L3
MIC1_R1
C231
2.2U/6.3V_6
MIC1_R2
R184
100/J_4
MIC1_R3
<Layout note>20091223
follow EMI suggestion , modify PIN6 from dummy to ADOGND
<20100309(C3A)>
Change L18,L21 from 0ohm to CX08T601000, for EMI issue.
CN4
MIC1_L3
L18
1A/600ohm_6
MIC1_L4
MIC1_R3
L21
1A/600ohm_6
MIC1_R4
ADOGND
1
2
6
3
4
C227
5
BLACK
D21
Normal
*14V/38V/100P_4
*470P/50V_4
Open Jack
2
*470P/50V_4
7
8
MIC1_JD#
C244
<20100309(C3A)>
Delete R380,R375 ; Chagne C415,C290 to R415,R416(0ohm),
Stuff R172,R183,R385, Add R417~R420(0ohm), for EMI issue.
<20100311(C3A)>
Change R415,R417 to shortpad, for layout issue
A
R186
2.2K/J_4
*0/short_6
*0/short_6
*0/short_6
SPK_L+_CH L23
C285
C280
1000P/50V_4 1000P/50V_4
MIC1_L1
1
*BAS316
SPK_MUTE#
A
<20100324(RAMP)>
Change R172,R183,R385,R416,R418~R420 to shortpad.
ADOGND
ADOGND
Quanta Computer Inc.
PROJECT : ZH9
Size
Document Number
Date:
Sunday, March 28, 2010
Rev
4A
AUDIO CODEC CX20672
1
f@
ho
tm
ai
l.c
om
2
in
3
xa
4
he
5
Sheet
19
of
40
5
4
3
2
USB(USB)
1
EMI(EMC)
+5VPCU
C165
4.7U/10V_6
+3VPCU
U19
IC(8P)G547E2P81U
8
IN1
OUT3
7
IN2
OUT2
6
OUT1
4
EN#
1
GND
9
5
GND-C OC#
R140
*10K/J_4
<25>
USB_EN#
USB_EN#
<Layout note>
Close to CONN
2A
C290
VIN_SRC
5VUSB_MB
2
3
<20100309(C3A)>
Add C290, for RF issue
C176
<Layout note>
Co-lay
USBOC#L <11>
0.1U/10V_4
Left
*0/short_4
+3VPCU
1
2
3
4
C222
C223
*0.1U/10V_4
1
*0/short_4
D30
*5V/30V/0.2P_4
*0.1U/10V_4
2
<20100324(RAMP)>
Delete L6,L11,L47 and change
R360,R361,R96,R99,R116,R118 to shortpad.
7
8
C471
C472
C473
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
+3VPCU
+3VPCU
+3VPCU
D
+3VPCU
+3VPCU
C474
C475
C476
C477
C478
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
+5VPCU
<20100303(C3A)>
Change back CN14,16,17(USB CONN) to DFHS04FR201.
+5VPCU
5VUSBPWR
2
3
<Layout note>
Co-lay
+ C330
100U/6.3V_3528
USBOC#R <11>
R96
*0/short_4
*0/short_4
C118
C128
D4
*5V/30V/0.2P_4
*0.1U/10V_4
2
*0.1U/10V_4
1
R99
+5VPCU
CN14
1
2
3
4
USBP6-_CN
USBP6+_CN
USBP6USBP6+
C481
C482
0.1U/10V_4
0.1U/10V_4
Upper Right
0.1U/10V_4
D5
*5V/30V/0.2P_4
VDD
GND6
DGND5
D+
GND1 GND7
GND8
USB_CONN
6
5
7
8
2
<11>
<11>
C133
1
USB_EN#
6
5
<20100128(B2A)>
Change CN14,16,17(USB CONN) from DFHS04FR201
to DFHS04FR362.
2A
U17
IC(8P)G547E2P81U
8
IN1
OUT3
7
IN2
OUT2
6
OUT1
4
EN#
1
GND
9
5
GND-C OC#
<20100324(RAMP)>
Delete C479,C480,C483, for ASSY issue.
+3VPCU
USB_CONN
D29
*5V/30V/0.2P_4
<20091202(A1A)_45485_sb800_scl_nda_1.04>
Reserve 0.1uF for USB P/N if trace <=10"
+5VPCU
VDD
GND6
DGND5
D+
GND1 GND7
GND8
2
R361
1
USBP0-_CN
USBP0+_CN
USBP0USBP0+
+3VPCU
CN17
D
<11>
<11>
<20100310(C3A)>
Add some 0.1uF to connect power plane, for RF issue.
+ C405
100U/6.3V_3528
R360
C362
4.7U/10V_6
+3V
0.1U/10V_4
+5VPCU
+5VPCU
+5VPCU
+5VPCU
C484
C485
C486
C487
C488
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
+5V
+5V
+5V
+5V
+5V
C
C
C489
C490
C491
C492
C493
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
5VUSBPWR
<Layout note>
Co-lay
C161
Lower Right
+ C394
0.1U/10V_4
R116
1
2
3
4
*0/short_4
C154
D6
*5V/30V/0.2P_4
*0.1U/10V_4
2
*0.1U/10V_4
C158
D7
*5V/30V/0.2P_4
VDD
GND6
DGND5
D+
GND1 GND7
GND8
USB_CONN
6
5
7
8
+5V
C497
C498
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
+3V
HOLE19
H-TC197BC157D126P2
C506
C507
0.1U/10V_4
0.1U/10V_4
*0.1U/10V_4
0.1U/10V_4
+1.5V
C517
C518
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
1
VIN
C523
0.1U/10V_4
0.1U/10V_4
VIN
VIN
VIN
VIN
1
1
HOLE16
*o-zh9-1
C524
C525
C526
C527
C528
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
HOLE2
*hg-te799x646be799x421d94p2
1
1
2
3
18
17
16
4
5
6
7
8
9
10
11
12
13
14
15
HOLE20
*O-ZH9-2
1
HOLE26
HG-TC236BC256D150P2
2
5
3
6
4
7
8
1
9
HOLE5
*HG-TE295X287BC276D94P2
2
5
3
6
4
7
1
2
3
4
5
27
26
25
24
23
A
1
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
8
1
9
<20100119(B2A)_ME Request>
Change Hole30 to NPTH
<20100122(B2A)>
Change all Hole's footprint for 凸凸
<20100125(B2A)>
Change Hole's footprint (HOLE12,HOLE25,HOLE1,HOLE2,HOLE20,PAD1) ; Delete HOLE3,HOLE4
<20100126(B2A)>
Change Hole's footprint (HOLE12)
<20100128(B2A)>
Change PAD2,Hole5,Hole12 footprint ; add two holes (Hole35,Hole36)
<20100129(B2A)>
Update Hole13,19,25~29 footprint.
<20100201(B2A)>
Delete the GND of Hole11 ; add a nut(MBFJ6002010) on Hole26 on BOT side.
<20100309(B2A)>
Change Hole26 footprint to HG-TC236BC256D150P2
HOLE1
*hg-e768x394d94p2
HOLE11
*H-C87D87N
Quanta Computer Inc.
PROJECT : ZH9
Size
4
Document Number
Rev
4A
USB on Board/LED/SW/HOLE
Date:
5
VIN
1
8
1
9
C522
8
1
9
HOLE6
*HG-TE354X315BC276D94P2-1
2
5
3
6
4
7
8
1
9
8
1
9
8
1
9
HOLE13
H-TC197BC157D126P2
HOLE12
hg-tc276be305x295d126p2
2
5
3
6
4
7
A
HOLE8
HOLE15
*HG-TE354X315BC276D94P2*HG-TE335X256BC276D94P2
2
5
2
5
3
6
3
6
4
7
4
7
PAD2
*emipad394X752np
1
HOLE31
*HG-C276D94P2
2
5
3
6
4
7
8
1
9
HOLE23
*HG-C276D94P2
2
5
3
6
4
7
8
1
9
8
1
9
HOLE7
*HG-C276D94P2
2
5
3
6
4
7
+1.5V
C516
VIN
HOLE36
*H-C118D118N
HOLE30
*H-O106X87D106X87N
1
HOLE29
H-TC197BC157D106P2
8
1
9
HOLE14
*HG-TC276BC256D94P2
2
5
3
6
4
7
+1.5V
C515
PAD1
*emipad394X752np
1
8
1
9
HOLE9
HOLE32
*HG-TE315X295BC276D94P2*HG-C276D94P2
2
5
2
5
3
6
3
6
4
7
4
7
HOLE21
HG-TC197BC295D126P2
2
5
3
6
4
7
1
8
1
9
8
1
9
8
1
HOLE34
*HG-C276D94P2
2
5
3
6
4
7
+3V
C505
B
HOLE27
H-TC197BC157D106P2
8
1
9
8
1
9
8
1
9
HOLE17
*HG-C276D94P2
2
5
3
6
4
7
8
1
9
HOLE22
*HG-C276D94P2
2
5
3
6
4
7
HOLE25
*hg-tc252be225x276d94p2
2
5
3
6
4
7
HOLE35
*H-C118D118N
HOLE28
H-TC197BC157D106P2
1
HOLE10
*HG-TE354X293BC276D94P2
2
5
3
6
4
7
+3V
C504
BOT(Thermal Hole)
8
1
9
HOLE33
*HG-C276D94P2
2
5
3
6
4
7
+5V
C496
+3V
1
HOLE24
HOLE18
HG-TC236BC276D130P2 HG-TC236BC276D130P2
2
5
2
5
3
6
3
6
4
7
4
7
8
1
9
B
BOT
(Mini-PCIe Hole)
Hole)
+5V
C495
+1.5V
HOLE(OTH)TOP(HDD
+5V
C494
<20100324(RAMP)>
Non-stuff C506, for interference issue
2
R118
1
USBP7-_CN
USBP7+_CN
USBP7USBP7+
+5V
CN16
100U/6.3V_3528
1
<11>
<11>
*0/short_4
3
2
Sunday, March 28, 2010
Sheet
1
20
of
40
4
3
+3V_LAN
AVDDH
*0/short_6
1
<Layout note>
Close to Pin40
L3
[email protected]/1A
DCR:0.15ohm
LX
C36
0.1U/16V_4
C45
1U/10V_4
2
C69
10U/10V_8
C28
1000P/50V_4
U1
1
D
C47
[email protected]/16V_4
C46
52SWR@1000P/50V_4
C30
52SWR@10U/10V_8
2
<10,23,24> PLTRST#
Int. PU in SB
3
<11,23> PCIE_WAKE#
VDDCT_REG
VDDCT
4
20mil
VDDCT
5
20mil
AVDDL
*52LDO@0/J_6
C40
0.1U/16V_4
2
C48
*52LDO@1U/10V_4
C42
0.1U/16V_4
1
2
R29
2
Y1
25MHz-LAN
C
33P/50V_4
AR8152
5X5mm
VDDCT
SMDATA
40-Pin QFN
AVDDL_REG
TESTMODE
SMBUS for debug
26
0.1u/10V_4
9
AVDDH_REG
TX_P
30
PCIE_RXP0_LAN
C10
0.1u/10V_4
RBIAS
AVDDL
31
TRXP0
REFCLK_N
12
TRXN0
REFCLK_P
33
13
NC
AVDDL
34
RBIAS
10
11
14
TRXP1
RX_P
35
TX1N
15
TRXN1
RX_N
36
16
17
<Layout note>
Close to LAN Chip
1nF reserved for EMI
49.9/F_4P2R
49.9/F_4P2R
1
3
RN1
DVDDL_REG
NC
LED0
PCIE_RXN0 <7>
PCIE_RXP0 <7>
AVDDL
C11
0.1U/16V_4
CLK_PCIE_LANP <10>
PCIE_TXP0 <7>
C13
0.1U/16V_4
PCIE_TXN0 <7>
DVDDL
37
LAN_ACTLED
38
NC
LED1
39
LAN_LINKLED#
NC
LX
40
LX
20
NC
GND
41
21
+3V_LAN
CLK_PCIE_LANN <10>
19
18
RN2
NC
4.7K/J_4
32
TX1P
<20100129(B2A)>
Non-stuff Y1,C43,C44 ; Stuff C67. Change the value of C43,C44 from
27pF to 33pF. (CLK for LAN from crystal change to internal CLK.)
R15
28
XTLI_LAN
1
3
C8
0.1U/16V_4
27
XTLO_LAN
<20100310(C3A)>
Stuff Y1,C43,C44 ; Non-Stuff C67. (14M_25M_48M_OSC is S0 plane,
doesn't support WoL.)
only
C7
TEST_RST
D
R414
*1K/J_4
25
PCIE_RXN0_LAN
XTLO
CLKREQ_LAN# <11>
DVDDL
29
TX0N
2
4
C44
SMCLK
*0/short_4
TX_N
2
4
1
33P/50V_4
DVDDL
VDDCT_REG
R412
24
XTLI
*3P/50V_4
C43
WAKEn
22
23
8
TX0P
XTLI_LAN
2
CLKREQn
7
2.37K/F_4
C34
0.1U/16V_4
AVDDH
PERSTn
XTLI_LAN
AVDDH
C33
1U/10V_4
PU in CLK Gen.
<20100303(C3A)>
Reserve R413,R414, for e-fuse.
R413
*4.7K/J_4
XTLO_LAN
20mil
C67
<10> CLK_25M_LAN
6
C41
1U/10V_4
1
C37
0.1U/16V_4
2
1
R35
1
VDDCT_REG
VDD33
C9
0.1U/16V_4
+3V_S5
Power Sequence:
VDD33 to PERSTn >= 100ms
20mil
1
R36
1
<Layout note>
Close to Pin1
76.1mA ; 30mil
+3V_S5
2
C19
0.1U/16V_4
C16
1U/10V_4
2
5
<BOM note>
If center tap power come from internal switch regulator
=>Stuff 52SWR@ (Default)
If center tap power come from internal LDO
<20100303(C3A)_FAE's suggestion>
=>Stuff 52LDO@
Change L3 from CV-4710MN03 to CV-4710TZ01.
C
40mil
NC
AR8152-AL1A-RL
AR8152-A : w/o 802.3az
AR8152-B : w/ 802.3az
C21
0.1U/16V_4
C18
*1000P/50V_4
C14
0.1U/16V_4
C15
*1000P/50V_4
+3V_S5
+1.1V analog power
+1.1V digital power
+2.7V analog power
+1.7V analog power
1
VDD33
31/34
AVDDL
24
DVDDL
22
AVDDH
5
VDDCT
ATHEROS
AR8152
AVDDL_REG
6
AVDDH_REG
9
DVDDL_REG
37
VDDCT_REG
4
LX
40
+1.1V regulator output (For all the analog 1.1V supply pins)
+2.7V regulator output (Connected to pin 22)
+1.1V regulator output (For all the digital 1.1V supply pins)
+1.8V regulator output (For VDDCT when LDO mode)
+1.7V Switching regulator (For VDDCT when switching mode)
B
B
RJ45
TRANSFORMER
CN10
C17
L2
*0/short_6
CX8EG601000: 0.5A/600ohm_6
C24
0.1U/16V_4
C26
C23
*1000P/50V_4
0.1U/16V_4
C25
*1000P/50V_4
AVDD_CEN
C22
1U/6.3V_4
TX0N
TX0P
8
7
6
5
4
3
2
1
TDTD+
CT
NC
NC
CT
RDRD+
TXTX+
CT
NC
NC
CT
RXRX+
9
10
11
12
13
14
15
16
X-TX1N
X-TX1P
TERM0
*0.1u/50V_8
LAN_ACTLED
LAN_ACTLED
R8
Active LED Pin:
Non-overclocking=>active high
TERM9
<20100125(B2A)>
Connect pin4,5,7,8 of CN10 to net
TERM9, for EMI and Safety issue
TERM1
X-TX0N
X-TX0P
R30
1nF reserved for EMI
510/J_6
8
NC/3+
X-TX1N
6
RX-/1-
TERM9
5
*0.1u/50V_8
NC2/2-
LAN_LINKLED#
4
NS0014 LF_Bothhand
C12
A
LINK LED Pin:
SWR mode=>active low
LDO mode=>active high
R18
R17
75/F_8
75/F_8
TERM9
LAN_LINKLED#
R7
*52LDO@0/J_8
R6
R5
52SWR@510/J_6
*52LDO@510/J_6
R4
*52SWR@0/short_8
X-TX1P
3
X-TX0N
2
X-TX0P
1
11
9
1000P/3KV_1808
NC1/2+
RX+/1+
TX-/0TX+/0+
GND
GND
14
13
GG+
RJ45-CONN
ho
tm
+3V_S5
<20100125(B2A)>
Change CN10 from DFTJ12FR069(SUY) to
DFTJ12FR066(FOX), for SMT issue.
NC4/3-
7
*[email protected]/J_8
C54
YY+
f@
Quanta Computer Inc.
Size
Document Number
LAN AR8152L
Date:
5
4
3
2
Sunday, March 28, 2010
xa
in
PROJECT : ZH9
he
VDDCT
TX1N
TX1P
12
10
l.c
om
5.1K/J_8
ai
R25
U13
Sheet
1
Rev
4A
21
of
40
A
5
4
3
2.5" SATA HDD(HDD)
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
17
18
19
20
21
22
23
24
D
2
1
<20100115(B2A)>
Change TX and RX pairs pin define for HDD can not be recognized.
CN21
SATA_TXP0 <12>
SATA_TXN0 <12>
SATA_RXN0 <12>
SATA_RXP0 <12>
D
5V_SATA
1A
R236
C460
C296
0.1U/10V_4
*0.1U/10V_4
10U/10V_8
+
C459
*0/short_8
+5V
C461
<20100303(C3A)>
Swap U23's pin1 and pin3, pin4 and pin6, for layout issue.
100U/6.3V_3528
<Layout note>
Close to CONN
U23
*CM1213-04SO
SATA_TXN0
SATA CONN
SATA_TXP0
1
CH1
2
VN
3
CH2
CH4
6
VP
5
CH3
4
SATA_RXP0
+5V
SATA_RXN0
C
C
CAPS LED
<20100203(B2A)>
Change R401 from CS13302JB21 to CS12702JB14
Change R402 from CS13302JB21 to CS14702JB28
Change R403 from CS13302JB21 to CS11202JB21
Change R404,R406 from CS13302JB21 to CS15602JB19
Change R405,R407 from CS13302JB21 to CS13602JB13
For LED's light issue.
NBSWON# <25>
D1
5.5V/25V/410P_4
power switch
+3V
<20100326(RAMP)>
Change R401 from CS12702JB14 to CS13302JB21
Change R404,R406 from CS15602JB19 to CS14702JB28
Change R403 from CS11202JB21 to CS12702JB14
Change R405,R407 from CS13602JB13 to CS12702JB14
For LED's light issue.
NUM LED
NBSWON#
2
1
1
+3V
SW1
3
4
5
6
2
LED/SW(UIF)
<20100125(B2A)>
Change SW1 from DHP00AC1G00 to DHP00533K00, for SMT issue.
<20091214(A1A)_Confirm with Acer Johnson_Yeh>
The JV01_NL and SJV01_NL had 4 LEDs --> Power / Battery / HDD / Communication
PWR indicator
LED2
2
1
R2
330/J_4
1
R1
330/J_4
LED_BLUE
LED1
2
LED_BLUE
+3V_S5
B
B
D37
LED6
3
HDD LED
R401
1
330/J_4
D31
D33
2 *5.5V/25V/410P_4
1
2 *[email protected]/25V/410P_4
1
LED3
PWR LED
SUS LED
SATALED# <12>
LED_BULE
2 *5.5V/25V/410P_4
1
3
2
R407
270/J_4
PWRLED# <25>
1
R406
470/J_4
SUSLED# <25>
LED_AMBER/BLUE
D36
1
2 *5.5V/25V/410P_4
D35
1
2 *5.5V/25V/410P_4
+3VPCU
LED5
3G LED
WLAN LED
3
2
R403
3G@270/J_4
1
R402
470/J_4
FULL LED
CHG LED
3G_LED# <23>
RF_LED# <23>
LED_AMBER/BLUE
D32
1
2 *5.5V/25V/410P_4
LED4
3
2
R405
270/J_4
BATLED0# <25>
1
R404
470/J_4
BATLED1# <25>
LED_AMBER/BLUE
D34
2 *5.5V/25V/410P_4
1
A
A
BT LED
ID(Left-->Right)
Power LED/BATT LED/HDD LED/WiFi LED
<LED spec>
BLUE：
Vf = 2.7~3.2V ； If = 5mA
BLUE/ORANGE：
BH→Vf = 2.7~3.7V ； If = 20mA
S2→Vf = 1.7~2.4V ； If = 20mA
Quanta Computer Inc.
max=25mA
max=25mA
PROJECT : ZH9
Size
4
Rev
4A
SATA HDD/LED/SW
Date:
5
Document Number
3
2
Sunday, March 28, 2010
Sheet
1
22
of
40
5
4
Mini Card(MPC)
3
2
+3V_Mini1_VDD
Turn off WLAN LED when 3G module is on
+3V_Mini1_VDD
+3V_Mini1_VDD
R422
RF_LED_ON
*0/J_4
PCIE_TXP1
PCIE_TXN1
<7> PCIE_RXP1
<7> PCIE_RXN1
15
13
11
9
7
5
3
1
<10> CLK_PCIE_MPC_P
<10> CLK_PCIE_MPC_N
<10> CLKREQ_MPC#
<25>
P80_DAT
P80_DAT
Q19
3
MINI-CARD1
MINI1_WAKE#
1
<11,21> PCIE_WAKE#
+3V_Mini1_VDD
GND
REFCLK+
REFCLKGND
CLKREQ#
Reserved
Reserved
WAKE#
UIM_VPP
UIM_RESET
UIM_CLK
UIM_DATA
UIM_PWR
+1.5V
GND
+3.3V
R399
52
50
48
46
44
42
40
38
36
34
32
30
28
26
24
22
20
18
R421
*10K/J_4
WLAN_LED#
*0/short_4
R392
WIMAX_LED#
C463
*0.1U/10V_4
WLAN_SDA0
WLAN_SCL0
C464
R394
R395
1
USBP2+
USBP2-
*0.1U/10V_4
*0/J_4
*0/J_4
3
RF_LED#
2
+3V_Mini1_VDD
R393
0.75A
*0/short_8
+3VSUS
<20100309(C3A)>
Add R421 and stuff R190, for purple LED issue
R400
*0/J_8
C468
C462
C467
C438
C434
*10U/10V_8
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
0.1U/10V_4
<22>
<20100122(B2A)>
Change Q20 from BAM00840001(PMOS) to BAM70020002(NMOS)
For LED cannot be full turn on issue.
<11>
<11>
0.5A
D
+1.5V
SB_SDATA0 <11,15>
SB_SCLK0 <11,15>
<20091202(A1A)_45485_sb800_scl_nda_1.04>
Reserve 0.1uF for USB P/N if trace <=10"
+1.5V_Mini1_VDD
R398
*0/J_8
C466
PLTRST#
RF_EN
R389
R390
R391
R396
R397
16
14
12
10
8
6
4
2
PLTRST# <10,21,24>
RF_EN <25>
*0/short_4
*0/short_4
*0/short_4
*0/short_4
*0/short_4
LFRAME#
LAD3
LAD2
LAD1
LAD0
*1000P/50V_4
<10,25>
<10,25>
<10,25>
<10,25>
<10,25>
Fun.
Model
WLAN
Atheros
AR9285(HB95)
WLAN
Broadcom
BCM94313
WLAN
Realtek
RTL8191SE
*2N7002K
R388
<25>
*0/short_4 3G_LED#
Q20
2N7002K
2
+3.3V
GND
+1.5V
LED_WPAN#
LED_WLAN#
LED_WWAN#
GND
USB_D+
USB_DGND
SMB_DATA
SMB_CLK
+1.5V
GND
+3.3Vaux
PERST#
W_DISABLE#
GND
GND
<7>
<7>
Reserved
Reserved
Reserved
Reserved
GND
+3.3Vaux
+3.3Vaux
GND
GND
PETp0
PETn0
GND
GND
PERp0
PERn0
GND
UIM_C4
UIM_C8
GND
D
51
49
47
45
43
41
39
37
35
33
31
29
27
25
23
21
19
17
0/J_4
0/J_4
54
R369
R370
<10> PCIRST#
<10> LCLK_DEBUG
53
P80_CLK
SDP_VIS
P80_CLK
SDP_VIS
+3V
RF_LED_EN
CN19
<25>
<25>
1
+1.5V_Mini1_VDD
*10K/J_4
+3V
+3VSUS
V
+1.5V
X
PCIE
X
USB
V
X
SMBUS
CLKREQ#
X
WAKE#
V
DISABLE#
X
V
C465
C469
*0.1U/10V_4
*10U/10V_8
PERST#
V
V
LED
SIZE
WLAN#
Half
WLAN#
Half
WLAN#
Half
V
X
X
(295mA)
V
X
X
V
V
V
V
C
C
+3VSUS
+1.5V_Mini2_VDD
Peak:2.75A
Normal:1.1A
+3V_Mini2_VDD
R192
*0/short_8
R205
*0/short_6
C255
C236
C274
C242
1
Mini Card 2(MNC)
C292
C293
C266
+3V_Mini2_VDD
2
3G@10U/10V_8 [email protected]/10V_4 [email protected]/10V_4 [email protected]/10V_4 [email protected]/10V_4 [email protected]/6.3V_4
+3V_Mini2_VDD
+3V
3G@10P/50V_4
+3V_Mini2_VDD
CN20
PCIE_TXP2
PCIE_TXN2
<7> PCIE_RXP2
<7> PCIE_RXN2
B
15
13
11
9
7
5
3
1
<10> CLK_PCIE_MNC_P
<10> CLK_PCIE_MNC_N
<11> CLKREQ_MNC#
P80_DAT
*3G@0/J_4
53
3G@MINI-CARD2
UIM_VPP
UIM_RST
UIM_CLK
UIM_DATA
UIM_PWR
+1.5V
GND
+3.3V
R190
<20100309(C3A)>
Stuff R190, for purple LED issue
C245
*[email protected]/10V_4
C249
*[email protected]/10V_4
R362
USBP4+ <11>
USBP4- <11>
PLTRST#_3G
R222
*3G@0/J_4PLTRST#
3G_EN
<25>
C264
*3G@1000P/50V_4
*[email protected]/10V_4
<20100119(B2A)>
Stuff R222 (EM770W: PERST# / Gobi2000: NC / F3307: NC)
<20100311(C3A)>
Non-stuff R222(CS00002JB38), for Huawei EM770W cannot be detected issue.
B
Fun.
UIM_VPP
UIM_RST
UIM_CLK
UIM_DATA
UIM_PWR
16
14
12
10
8
6
4
2
C237
Model
+3V
+3VSUS
3G
Qualcomm
Gobi2000
X
3G
HUAWEI
EM770W
X
(2.75/1.1A)
3G
Option
GTM382
X
(2.75/1.1A)
3G
Ericsson
F3307
X
(2.75/0.99A)
Intel
5150(512...)
X
(643mA)
V
+1.5V
PCIE
X
X
X
X
X
X
X
X
USB
UIM
UIM_Vpp
SMBUS
CLKREQ#
WAKE#
PERST#
LED
PCM
SIZE
V
V
X
X
X
X
V
X
WWAN#
V
V
X
X
X
X
V
V
WWAN#
V
V
X
X
X
X
V
V
WWAN#
Full
X
V
V
X
X
X
X
V
X
WWAN#
Full
V
V
X
X
X
V
V
V
V
WLAN#
WWAN#
Full
Full
V
V
Full
V
V
V
1
2
3
4
5
UIM_PWR
UIM_VPP
UIM_RST
UIM_DATA
UIM_PWR
C60
3G@27P/50V_4
UIM_DATA
C63
3G@10P/50V_4
UIM_CLK
C64
3G@10P/50V_4
UIM_RST
C62
3G@27P/50V_4
UIM_VPP
C61
3G@33P/50V_4
<20090604(A1A)_Qualcomm design guide>
Place 0.1uF near connector's VCC pin
+3V
U3
UIM_RST
1
CH1
2
UIM_CLK
VN
3
CH2
CH4
VP
CH3
6
UIM_VPP
5
4
UIM_PWR
A
C68
3G@1U/10V_6
C59
[email protected]/10V_4
ai
*[email protected]/10V_4
3G@SIM-Conn
<20091202(A1A)_45485_sb800_scl_nda_1.04>
Reserve 0.1uF for USB P/N if trace <=10"
UIM_DATA
3
2
he
4
xa
Date:
Quanta Computer Inc.
PROJECT : ZH9
Document Number
f@
in
Size
ho
*3G@CM1293-04SO
5
DISABLE#
tm
*[email protected]/10V_4
GND(C5)
VCC(C1)
VPP(C6)
RST(C2)
DATA(C7)
GND
GND
C65
GND
GND
C66
*3G@0/J_8
<20091202(A1A)_45485_sb800_scl_nda_1.04>
Reserve 0.1uF for USB P/N if trace <=10"
12
14
USB-_SIM
USB+_SIM
+1.5V_Mini2_VDD
Max: 7.5mA (Option)
CLK(C3)
D-(C8)
D+(C4)
CT
CD
13
11
<11>
<11>
0.5A
+1.5V
3G_LED# <22>
l.c
om
JSIM1
A
*3G@0/J_6
<20100303(C3A)>
Change JSIM1 footprint from sim-ce01x-3-14p
tosim-ce01x-3-14p-smt, for SMT open issue.
MultiMedia SIM
6
7
8
9
10
*3G@0/J_8
R215
10K/J_4
WLAN_LED#
3G_LED#
Wimax
UIM_CLK
R208
2
R235
<25> 3G_WAKE_2
GND
REFCLK+
REFCLKGND
CLKREQ#
Reserved
Reserved
WAKE#
52
50
48
46
44
42
40
38
36
34
32
30
28
26
24
22
20
18
1
<7>
<7>
*3G@0/J_4
+3.3V
GND
+1.5V
LED_WPAN#
LED_WLAN#
LED_WWAN#
GND
USB_D+
USB_DGND
SMB_DATA
SMB_CLK
+1.5V
GND
+3.3Vaux
PERST#
W_DISABLE#
GND
GND
R188
3G_WAKE
Reserved
Reserved
Reserved
Reserved
GND
+3.3Vaux
+3.3Vaux
GND
GND
PETp0
PETn0
GND
GND
PERp0
PERn0
GND
UIM_C4
UIM_C8
54
<25>
51
49
47
45
43
41
39
37
35
33
31
29
27
25
23
21
19
17
GND
P80_CLK
SDP_VIS
Rev
4A
Mini-Card/WL/3G/SIM
Sheet
Sunday, March 28, 2010
1
23
of
40
5
4
3
2
AU6437B52-GBL-GR (MMC)
1
4 IN 1 CARD READER (MMC)
CN6
D
T92
R382
+3V
XTALSEL
CRMD_N
NBMD
CTRL1/SD_WP/XD_CLE
CTRL3/SD_CD#/XD_WE#
DATA1
DATA0
DATA7
DATA6
32mA
+1.8V_CARD
R381
*0/J_4
CTRL2/SD_CMD/XD_RDY
CTRL4/MS_INS#/XD_RE#
XD_CE#
CTRL1/SD_WP/XD_CLE
CTRL0/XD_ALE/MS_BS
CTRL3/SD_CD#/XD_WE#
XD_WP#
DATA0
DATA1
SD_DATA2
SD_DATA3
CTRL2/SD_CMD/XD_RDY
T91
*0/short_4 +3V_CR
XTALSEL
C453
Clock input selection
'1' for 48MHz input [Default]
'0' for 12MHz input
0.1U/16V_4
+3.3V: 43mA
VCC_XD
+3V_CR
C444
*0/short_4
*0/short_4
CLK_48M_CR_R
CARD_RST#
R384
330/J_4
+3V_CR
C458
USBP1+
USBP1-
C446
4.7U/10V_6
*0.47U/16V_6
XI
XO
+1.8V_CARD
<20091202(A1A)_45485_sb800_scl_nda_1.04>
Reserve 0.1uF for USB P/N if trace <=10"
USBP1+
USBP1C454
C457
*0.1U/16V_4
*0.1U/16V_4
B
C451
4.7U/10V_6
XI
*18P/50V_4
1
C455
2
Y5
*12MHz-CR
C456
<20100129(B2A)>
Non-stuff Y5,C455,C456 ; Stuff R383. (CLK for
Cardreader from crystal change to internal CLK.)
48
47
46
45
44
43
42
41
40
39
38
37
GPON7
EXT48IN
RSTN
REXT
VD33P
DP
DM
VS33P
XI
XO
VDD
VDD
XO
*18P/50V_4
XD-R/B
XD-RE
XD-CE
XD-CLE
XD-ALE
XD-WE
XD-WP
XD-D0
XD-D1
SD-DAT2
SD-DAT3
SD-CMD
4IN1-GND1
MS-VCC 45mA
MS-SCLK
MS-DATA3
MS-INS
MS-DATA2
MS-DATA0
CTRL0/XD_ALE/MS_BS
CTRL0
DATA5
CTRL2
GPI4
DATA4
DATA3
AU6437B52-GBL-GR
DATA2
XDWPN
GPI2
XDCEN
EEPDATA
GPI1
36
35
34
33
32
31
30
29
28
27
26
25
DATA5
CTRL2/SD_CMD/XD_RDY
GPI4
DATA4
T88
DATA3
DATA2
XD_WP#
GPI2
XD_CE#
T86
EEPDATA
GPI1
T89
T87
DATA0
R218
*0/short_4
SD_DATA0
DATA1
R214
*0/short_4
SD_DATA1
MS-DATA1
MS-BS
4IN1-GND2
SD-VCC
SD-CLK
SD-DAT0
XD-D2
XD-D3
XD-D4
SD-DAT1
XD-D5
XD-D6
XD-D7
XD-VCC
XD-CD-SW
SD-WP-SW
SD-CD-SW
20
21
22
23
24
25
26
27
28
29
30
31
32
33
34
35
36
SHIELD1-GND
SHIELD2-GND
SHIELD3-GND
SHIELD4-GND
37
38
41
42
23mA
D
DATA1
CTRL0/XD_ALE/MS_BS
VCC_XD
VCC_XD
SD_CLK
SD_DATA0
DATA2
DATA3
DATA4
SD_DATA1
DATA5
DATA6
DATA7
XD_CD#
CTRL1/SD_WP/XD_CLE
CTRL3/SD_CD#/XD_WE#
R229
5.1K/J_4
<Layout note>
Close to pin41 of connector
C
CONN_CARDREADER
DATA2
R232
*0/short_4
SD_DATA2
DATA3
R231
*0/short_4
SD_DATA3
<Layout note>
Close to Connector
<Layout note>
Close to pin5 of connector
VCC_XD
CTRL0/XD_ALE/MS_BS
R212
*0/short_4
SD_CLK
C262
C282
4.7U/10V_6
C263
*10P/50V_4
T90
VCC_XD
<11>
<11>
VDDH
GND
VDD
XTALSEL
TRIST
NBMD
CTRL1
CTRL3
DATA1
DATA0
DATA7
DATA6
1
2
3
4
5
6
7
8
9
10
11
12
<Layout note>
Close to connector
CTRL0 trace length shorter ,
surround with GND.
V18
CF_V33
AVDD5V
AGND5V
V33
VDDHM
GND
VDD
CTRL4
XDCDN
SDWPEN
EEPCLK
<11> CLK_48M_CR
<10,21,23> PLTRST#
R383
R386
13
14
15
16
17
18
19
20
CTRL4/MS_INS#/XD_RE# 21
XD_CD# 22
23
EEPCLK 24
R387
*100K/J_4
VCC_XD
+3V
C
U22
0.1U/16V_4
<EMI>
1
2
3
4
5
6
7
8
9
10
11
12
13
14
MS_SCLK
15
DATA3
16
CTRL4/MS_INS#/XD_RE# 17
DATA2
18
DATA0
19
SD write protect
1:decided by SDWP[Default]
0:letting SD always
write-able
*0/J_4
CTRL1/SD_WP/XD_CLE
R225
*0/short_4
0.1U/16V_4
MS_SCLK
B
C277
*10P/50V_4
R374
+1.8V_CARD
+3V_CR
C445
<EMI>
0.1U/16V_4
C447
C452
4.7U/10V_6
C450
2.2U/6.3V_6
0.1U/16V_4
+3V_CR
USBP1+
USBP1-
C448
C449
*2.2P/50V_4
*2.2P/50V_4
A
A
Quanta Computer Inc.
PROJECT : ZH9
Size
Document Number
Rev
4A
AU6437 (Card Reader)
Date:
5
4
3
2
Sunday, March 28, 2010
Sheet
1
24
of
40
5
4
1A/22ohm_6
C232
0.1U/16V_4
0.1U/16V_4
0.1U/16V_4
0.1U/16V_4
0.1U/16V_4
D
<20090831(A1A)_EC team suggest>
1.remove diode from EC_SCI#
<11>
GA20
121
<11>
KBRST#
122
<11>
EC_SCI#
29
EC_FPBACK#
<16> EC_FPBACK#
T48
E_KEY
124
A_RST#_SB
<10> A_RST#_SB
7
123
<20> USB_EN#
<10>
<11>
C
R158
*22/J_4
C205
*10P/50V_4
SDP_VIS
<23>
P80_CLK
<23>
P80_DAT
SDP_VIS
R166
*0/J_4
MY9
P80_CLK
R165
*0/J_4
MY10
P80_DAT
R164
*0/J_4
MY11
9
<18>
<18>
<18>
<18>
<18>
<18>
<18>
<18>
MX0
MX1
MX2
MX3
MX4
MX5
MX6
MX7
<18>
<18>
<18>
<18>
<18>
<18>
<18>
<18>
<18>
<18>
<18>
<18>
<18>
<18>
<18>
<18>
MY0
MY1
MY2
MY3
MY4
MY5
MY6
MY7
MY8
MY9
MY10
MY11
MY12
MY13
MY14
MY15
<26>
MBCLK
<26>
MBDATA
<4> 2ND_MBCLK
<4> 2ND_MBDATA
<18>
TPCLK
<18>
TPDATA
<29,30,32> +1.8V_ON
<18> BT_POWERON#
<29,30,32,33> MAINON
B
125
EC_SMI#
LCLK_EC
<23>
SERIRQ
SERIRQ
<EMI>
<10> RTC_CLK
6
R199
LFRAME
LAD0
LAD1
LAD2
LAD3
LCLK
GPIO11/CLKRUN
GPIO24/LDRQ
GPIO10/LPCPD
LREST
GPIO67/PWUREQ
SERIRQ
GPIO65/SMI
GPIO
MY0
MY1
MY2
MY3
MY4
MY5
MY6
MY7
MY8
MY9
MY10
MY11
MY12
MY13
MY14
MY15
53
52
51
50
49
48
47
43
42
41
40
39
38
37
36
35
34
33
KBSOUT0/JENK
KBSOUT1/TCK
KBSOUT2/TMS
KBSOUT3/TDI
KB
KBSOUT4/JEN0
KBSOUT5/TDO
KBSOUT6/RDY
KBSOUT7
KBSOUT8
KBSOUT9/SDP_VIS
KBSOUT10/P80_CLK
KBSOUT11/P80_DAT
KBSOUT12/GPIO64
KBSOUT13/GPIO63
KBSOUT14/GPIO62
KBSOUT15/GPIO61/XOR_OUT
GPIO60/KBSOUT16
GPIO57/KBSOUT17
70
69
67
68
GPIO17/SCL1
GPIO22/SDA1
GPIO73/SCL2
GPIO74/SDA2
*0/short_4 RTC_CLK_EC
77
79
GPIO01/TB2
GPIO03
GPIO06
GPIO07
GPIO23/SCL3
GPIO30/CIRTX2
GPIO31/SDA3
GPIO32/D_PWM
GPIO33/H_PWM
GPIO36
GPIO40/F_PWM
GPIO42/TCK
GPIO43/TMS
GPIO44/TDI
GPIO45/E_PWM
GPIO46/CIRRXM/TRST
GPO47
GPIO50/TDO
GPIO51
GPIO52/CIRTX2/RDY
GPIO53
GPIO81
GPO82/TEST
GPO84/TRIST
GPIO41
64
95
93
94
119
109
120
65
66
15
16
17
20
21
22
23
24
25
26
27
28
91
110
112
80
GPIO56/TA1
GPIO20/TA2
GPIO14/TB1
31
117
63
GPIO15/A_PWM
GPIO21/B_PWM
GPIO13/C_PWM
GPIO66/G_PWM
32
118
62
81
LPC
ECSCI/GPIO54
KBSIN0
KBSIN1
KBSIN2
KBSIN3
KBSIN4
KBSIN5
KBSIN6
KBSIN7
72
71
10
11
12
13
GPI94/DA0
GPI95/DA1
GPI96/DA2
GPI97
D/A
54
55
56
57
58
59
60
61
TPCLK
TPDATA
TIMER
PS/2
GPIO77
GPO76/SHBM
GPIO75
SPI
GPIO72/IRRX1/SIN2
GPIO70/IRRX2_IRSL0
GPIO71/IRTX/SOUT2
GPIO87/CIRRXM/SIN_CR
GPIO34/CIRRXL
GPIO16/CIRTX
GPO83/SOUT_CR/XORTR
SMB IR
GPIO37/PSCLK1
GPIO35/PSDAT1
GPIO26/PSCLK2
GPIO27PSDAT2
GPIO25/PSCLK3
GPIO12/PSDAT3
F_SDI
F_SDO
F_CS0
F_SCK
FIU
GPIO00/32KCLKIN
GPIO55/CLKOUT
GPIO02
NPCE781L(A0DX)
97
98
99
100
108
96
101
105
106
107
KBRST/GPIO86
MX0
MX1
MX2
MX3
MX4
MX5
MX6
MX7
MBCLK
MBDATA
2ND_MBCLK
2ND_MBDATA
GPI90/AD0
GPI91/AD1
GPI92/AD2
GPI93/AD3
GPIO05
GPIO04
A/D
GPIO85/GA20
TEST# XORTR# TRIST#
no test mode selected (normal operation)
1
X
X
XOR-tree test mode
0
0
1
ICT mode
0
1
Reserved exclusively for Nuvoton use
0
+3V
4.7U/6.3V_6
TEMP_MBAT <26>
C239
0.01U/16V_4
R187
E781AGND
VCC_POR
VREF
E781AGND
TPD_TRIP
ICMNT
T49
HDMI_SENSE
<26>
SHBM
C233
3300P/50V_4
E781AGND
TEST#
R177
*10K/J_4
XORTR#
R175
*10K/J_4
RF_LED_EN
R173
*10K/J_4
3G_EN
R200
10K/J_4
E781AGND
t
T50
*100K/F(NTC)_4
ACIN
<26>
NBSWON# <22>
LID#
<16>
SUSB# <11>
BATLED0#
BATLED1#
SM BUS PU
Plam Rest
Thermal Sersor
SUSLED#
+3VPCU
MBCLK
MBDATA
R198
R197
4.7K/J_4
4.7K/J_4
2ND_MBCLK
2ND_MBDATA
R195
R196
4.7K/J_4
4.7K/J_4
+3V
BATLED0# <22>
BATLED1# <22>
VRON <28,33>
SUSLED# <22>
1ST: Battery
2ND: CPU Thermal Sensor / DTS
3RD: VGA Thermal Sensor
AMP_MUTE# <19>
CPUFAN# <4>
3G_WAKE <23>
VIN_ON <26>
D/C#
<26>
S5_ON <27,31,34>
HDMI_HPD_EC# <17>
+3VPCU
BATLED0#
BATLED1#
<20090831(A1A)_EC team suggest>
DNBSWON# <11> 1.remove diode from DNBSWON#
TEST#
RF_LED_EN <23>
3G_WAKE_2 <23>
3G_WAKE_2
D
RT1
R193
R194
C
100K/J_4
100K/J_4
<20090831(A1A)_EC team suggest>
1.change R7027/R7028 to 1M or 100K ohm
2.change PWR/SUS LED's power from +3VPCU to +3V_S5 or +3VSUS
can reduce pull-high resistor of SUSLED#/PWRLED#
SUSON <30,33>
FANSIG <4>
CONTRAST <16>
PWRLED#
PWRLED# <22>
SPI FLASH
+3VPCU
84
83
82
3G_EN
<23>
U9
R224
SPI_SDI_uR
75
73
74
113
14
114
111
RF_EN
86
87
90
92
SPI_SDI_uR
SPI_SDO_uR
SPI_CS0#_uR
SPI_SCK_uR
30
ECDB_CLOCK
T46
85
VCC_POR#
R209
104
+A3VPCU
EC_RSMRST# <11>
SUSC# <11>
ECPWROK <11>
RF_EN <23>
22/J_4
R228
+3VPCU
HWPG
10K/J_4
SPI_SDI_uR_R
2
SO
SPI_SDO_uR_R
5
SI
SPI_SCK_uR_R
6
SPI_CS0#_uR
1
XORTR#
R210
22/J_4 SPI_SDO_uR_R
R211
22/J_4 SPI_SCK_uR_R
47K/J_4
+3VPCU
8
VDD
HOLD
SCK
WP
7
C273
3
0.1U/16V_4
CE
VSS 4
W25Q80BVSSIG_8Mbits
1/13 Comfirm by vendor mail :
If the Southbridge enables 'Long Wait Abort' by default, the
flash device should be 50MHz (or faster)
<20090721_FAE suggestion>
Stuff 100K and close to EC side
for improving power consumption
HWPG
<20100319(RAMP)>
Non-stuff D9,D17, for cost down.
B
+3V
R170
<33> HWPG_VDDR
SPI_SDI_uR
<29> HWPG_NB_CORE
<30> HWPG_1.5V
R201
<31> HWPG_1.1V
100K/J_4
C220
L19
<32,33> HWPG_1.8V
1U/10V_4
<27> HWPG_SYS
1A/22ohm_6
<28> CPU_COREPG
E781AGND
0
00 or 11
SHBM=0: Enable shared memory with host BIOS
*47K/J_6
T53
1
8
CLKRUN#
U6
GND1
GND2
GND3
GND4
GND5
GND6
<10>
DS page248, GA20/KBRST# are VCC well, but
they were held low when VDD well is off.
3
126
127
128
1
2
LFRAME#
LAD0
LAD1
LAD2
LAD3
LCLK_EC
C189
0.1U/10V_4
5
18
45
78
89
116
<10,23>
<10,23>
<10,23>
<10,23>
<10,23>
<10>
C171
1
4.7U/6.3V_6
R191
100K/F_6
BAS316
2
C224
TEST Mode
2
2
C221
1
VDD
C204
VCORF
C250
AGND
C251
102
C225
VCC1
VCC2
VCC3
VCC4
VCC5
<20090602(A1A)_Vendor suggest>
Add 2.2ohm series resister for
ESD/EOS issue
+3V_VCC_EC
I/O ADDRESS SETTING
D8
+3V_VDD_EC
AVCC
2.2/J_6
E781AGND
19
46
76
88
115
R203
E781AGND
4.7U/6.3V_6
+3VPCU
*0/J_6
+3V
<Layout note>
Place every 0.1uF
close to every
power pin
VCORF_uR 44
30mA
R155
10mA
1
4
0.1U/16V_4
+3VPCU
2
<20090602(A1A)_Vendor suggest>
Place 10nF-0.1uF capacitors for
every AD input. And close to the AD
input.
+A3VPCU
C228
103
L20
EC(KBC)
3
D10
BAS316
D13
BAS316
D9
*BAS316
D15
BAS316
D16
BAS316
D17
*BAS316
D14
BAS316
10K/J_4
HWPG_R
R169
HWPG
*0/short_4
E781AGND
INTERNAL KEYBOARD STRIP SET
10K/J_10P8R
1 MX3
2 MX2
3 MX1
4 MX0
5
f@
ho
+3VPCU
10K/J_4
he
xa
R171
Size
4
3
2
PROJECT : ZH9
Document Number
Rev
4A
NPCE781L & FLASH
Date:
5
Quanta Computer Inc.
in
+3VPCU
MY0
A
ai
RP5
10
9
8
7
6
tm
MX4
MX5
MX6
MX7
A
l.c
om
+3VPCU
Sheet
Sunday, March 28, 2010
1
25
of
40
4
3
VA
PL2
HI0805R800R-00/5A/80ohm_8
PJ2
2
PD4
PDS1040S-13
1
1
2
1
2
3
VA2
3
5
1
VIN_SRC
PQ30
AOL1413
EC3
2
5
2200P/50V_4
PC44
PC40
0.1U/50V_6
PC39
0.1U/50V_6
PR62
220K/F_6
CSIP_1
4
PL1
HI0805R800R-00/5A/80ohm_8
PC41
0.1U/50V_6
VIN_SRC
PC45
0.1U/50V_6
PC38
0.1U/50V_6
*0.1U/50V_6
0.1U/50V_6
PD3
SMAJ20A
1
PR60
220K/F_6
EC2
2
5
3
4
*0/short_6
D/C#
<25>
PQ3
IMD2AT108
VIN_SRC
D
PR24
10K/J_6
6
PR59
2
PD5
SW1010CPT
PR19
33K/J_6
2200P/50V_4
3
PC37
0.1U/50V_6
D
EC1
1
2
3
1
7
6
5
4
2200P/50V_4
0.01_3720
PR64
PQ6
AOL1413
2
PC36
3
1
4
5
POWER_JACK
dcjk-2dc2003-000111-3p-v
2
PQ1
DMN601K-7
1
CSIP_1
VIN_SRC
PC121
1U/10V_4
PR166
10/F_6
PR18
10/F_6
PC19
2200P/50V_4
PR163
4.7/J_6
PC8
0.1U/25V_4
PC111
1U/10V_4
ISL88731_VDDP
PC15
0.1U/50V_6
21
26
27
CSIN
1
33
32
31
30
28
CSIP
C
11
MBDATA
PR25
49.9/F_4
88731ACSET
24
10
SCL
PHASE
23
ISL88731_PHASE
ACOK
LGATE
20
22
PR164
22K/F_4
VREF
4
ICOMP
PR150
2.21K/F_4
PC2
0.1U/25V_4
PR5
100/J_4
4 S2
5
1
PC96
0.01U/25V_4
ICMNT
47P/50V_4
PC105
0.01U/25V_4
PC106
2200P/50V_4
PC114
2200P/50V_4
PC118
PC117
10U/25V_1206
BAT-V
B
CSOP_1
PR153
10/F_6
GND
29
BAT-V
BAT-V
VIN_SRC
PU8
ISL88731A
5
PR63
150K_4
ISL88731 thermal pad
tie to Pin12
ICMNT
VIN
PQ5
AOL1413
1
2
3
<25>
PR6
100/J_4
PC42
1u/25V_6
MBCLK
PC104 PC102
0.01U/25V_4 *0.01U/25V_4
<25>
PR61
39K_4
PU1
CM1293A-04SO
MBDATA
<25>
1
TEMP_MBAT
CH1
2
VN
3
CH2
CH4
6
VP
5
CH3
4
A
MBDATA
3
A
BAT-V
2
PR160
2.2/F_4
PC4
PC108
*1U/10V_4
47P/50V_4
6
4
PC3
15
GND
TEMP_MBAT <25>
NC
TEMP_MBAT_C
VBF
VCOMP
14
6
100/J_4
7
PR152
100/J_4
ICM
PR7
S1/D2
3 G2
CSOP_1
17 CSON
PR151
*0/short_4
16
NC
8
5
2 D1
0.01_3720
PR159
PL5
6.8uH/4.5A_7X7X3
PC107
0.1U/25V_4
NC
HI0805R800R-00/5A/80ohm_8
PL3
BAT-V
MBAT+
8
10U/25V_1206
ACIN
NC
8
7
6
5
4
3
2
10 1
CSOP
18 CSOP
G1
PR155
10/F_6
7
Batt_Conn
PJ1
19
1 D1
PQ33
DCIN
3
C
AO4932
ISL88731_LGATE
PGND
CSON
HI0805R800R-00/5A/80ohm_8
PL4
9
2
PC1
100P/50V_4
B
VDDP
VCC
UGATE
PR157
82.5K/F_4
PR8
*0/short_4
PC122
0.1U/50V_6
88731B_1
SDA
PC12
0.1U/25V_4
DCIN
PR22
2.7/J_6
88731B_2
25
9
13
ACIN
BOOT
12
<25>
VDDSMB
ISL88731_UGATE
PR149
100K/F_4
MBCLK
CSSN
NC
GND
GND
GND
GND
CSSP
PC95
0.1U/25V_4
+3VPCU
PC171
4.7U/25V_8
PD15
*RB500V-40
+3VPCU
+3VPCU
MBCLK
<25>
VIN_ON
2
Quanta Computer Inc.
PQ4
DMN601K-7
PROJECT : ZH9
1
Add ESD diode base on EC FAE suggestion
Size
Document Number
Rev
4A
CHARGER (ISL88731)
Date:
5
4
3
2
Sheet
Sunday, March 28, 2010
1
26
of
40
5
4
MAIND
SUSD
MAIND
<30,33>
SUSD
<31,33>
3
PR124
*0/short_4
2
1
VL
1
<4,34> SYS_SHDN#
VIN_SRC
PR128
39K/F_4
PC90
4.7U/6.3V_6
3V5V_EN
PC153
2200P/50V_4
PC162
*10u/25V_1206
PC158
4.7U/25V_8
5V_EN
PC152
0.1U/50V_6
PR129
*0/short_4
PR135
*0/short_4
PR131
*0/J_4
PR126
*0/short_4
PR133
390K/J_4
3V_EN
PR123
*0/short_4
PC87
1U/10V_4
PC89
0.1U/25V_4
PC156
0.1U/50V_6
PR125
*0/J_4
PC88
0.01U/25V_4
PC86
0.1U/25V_4
REF
PC157
2200P/50V_4
PC163
*10U/25V_1206
PQ46
FDMC8884
5
PR127
3
2
1
PR185
2.2/F_4
PR117
*0/J_4
PC154
PD10
SX34
PC149
4
PC79
0.1U/50V_6
1
2
3
PC155
2200P/50V_4
PR114
*0/short_4
10U/25V_1206
5V_DL
PQ44
FDMC8296
35
34
33
PC150
5
PR112
PR106
1/F_6
+3VPCU
PR122
REFIN2 137K/F_4
5
32
31
30
29
28
27
26
25
REFIN2
ILIM2
OUT2
SKIP#
PGOOD2
EN2
DH2
LX2
PU7
RT8206
PL13
3.3uH/6A_7X7X3
SKIP
DDPWRGD_R
3V_EN
PR113
2.2/F_4
C
PD13
SX34
PC85
+
4
PR119
*0/J_4
PC80
2200P/50V_4
3
2
1
5V_LX
BYP
OUT1
FB1
ILIM1
PGOOD1
EN1
DH1
LX1
PAD
PAD
PAD
PAD
PAD
+5VPCU
+3VPCU
4
330U/6.3V_7343
9
10
11
12
133K/F_4 DDPWRGD_R 13
5V_EN 14
15
16
37
36
LDOREFIN
LDO
VIN
NC
ONLDO
VCC
TON
REF
+5VPCU
1
2
3
PL12
2R2uH/8A_7X7X3
+
3V_DH
3V_LX
PC83
0.1U/50V_6
PQ45
FDMC8296
BST1
DL1
PVCC
NC
GND
PGND
DL2
BST2
5V_DH
PC82
0.1U/50V_6
PR111
1/F_6
17
18
19
20
21
22
23
24
4
C
*0/J_4
8
7
6
5
4
3
2
1
PR132
150K/J_4
PQ43
FDMC8884
+5VPCU
D
VL
5
VIN_SRC
2
D
PR115
*0/short_4
PR120
*0/J_4
3V_DL
0.1U/50V_6
PR101
*0/J_4
330U/6.3V_7343
2
PD11
CHN217UPT
PR137
*0/short_6
VL
PC74
0.1U/50V_6
SKIP
PR130
*0/J_4REF
PR134
*0/short_4
PR121
*0/J_4
PC75
1U/10V_4
3
1
+3VPCU
PC73
1U/25V_6
PC76
0.1U/50V_6
2
PD12
CHN217UPT
B
+15V
PR102
*0/short_4
3
PR136
*100K/F_4
1
PR105
22/J_8
B
PC78
DDPWRGD_R
HWPG_SYS <25>
1U/25V_6
PR138
*0/short_4
VIN_SRC
+15V
+3V_S5
+3VPCU
+5VPCU
3
+3VPCU
+3VPCU
2
5
PR141
1M/J_6
PQ22
AO3404
1
3
PR143
22/J_8
5
SUSD
PR139
1M/J_6
PQ23
DMN601K-7
PQ29
DMN601K-7
l.c
om
1
2
3
PQ20
AON7410
+3VSUS
A
ho
Quanta Computer Inc.
+3V
PROJECT : ZH9
Size
Document Number
in
+5V
Rev
4A
xa
+3V_S5
f@
1
PR146
1M/J_6
PC92
1000P/50V_4
4
ai
2
1
PQ24
DTC144EU
1
2
PQ21
AO3404
PQ47
AON7410
tm
2
1
A
SYSTEM 5V/3V (RT8206B)
Date:
5
4
3
2
he
<25,31,34> S5_ON
MAIND
4
1
2
3
MAIND
2
3
3
3
S5D
Sunday, March 28, 2010
Sheet
1
27
of
40
5
4
3
2
1
PR37
49.9/0.1%_6
CPU_CORE
8380CSN1
8380CSP1
PR27
665/F_4
SNS_NEG_VDD_0
PR13
<25,33>
*0/short_4
VRON
PC119
470P/50V_4
+1.5V
PR204
*330/F_4
PQ9
*AO3402
PR205
*1K/F_4
2
8380RSN1
PR47
*0/short_4
PR34
665/F_4
PR169
49.9/0.1%_6
PC115
100p/50V_4
2
1
+3V
PR167
27K/F_4
5
PC6
1000p/50V_4
1
2
3
33
34
PR46
43.2K/F_4
PC130
1000p/50V_4
OZ8380
2
1
2
3
T54
PC131
1000P/50V_6
CPU_SVD
PC100
1u/6.3V_4
+5VPCU
8380HDR2
2
+5VPCU
8380LDR2
+3V
<4>
CPU_SVC
CPU_SVC
8380SVD
PR26
PR38
1 D1
G1
8
2 D1
S1/D2
7
3 G2
6
4 S2
5
PC170
PC172
4.7U/25V_8
*10U/25V_1206
PL6
1uH
8380VREF
2
PQ31
AO4932
1
<25>
PC113
1000P/50V_6
VIN
PR154
27K/F_4
PR21
+
Close to Phase
Inductor
4.22K/F_4
PC94
330u/2V_7343
PC101
10u/25V_1206
PR170
10K_6_NTC
PR162
4.99K/F_4
PR158
2.2/F_4
PC116
PC103
1000p/50V_4
68n/25V_6
PC120
220p/50V_4
PR23
CPU_VDDNB_CORE
PR171
4.99K/F_4
PR165
T57
B
2
1.2K/F_4
*0_4
OCP: 3A
1.5A
T56
2.2/F_6
CPU_COREPG
PR29
49.9/0.1%_6
<4> CPU_VDDNB_FB_H
PC10
330u/2V_7343
1
PR168
32.4K/F_4
SNS_NEG_VDD_1
VIN
PC93
0.1u/50V_6
PR12
PR10
1.91K/F_4
8380SVC
*0/short_4
B
T5
+
PC11
330u/2V_7343
PD1
RB501V-40
PC98
0.22u/25V_6
PC127
470P/50V_4
C
+
8380LDR1
PR4
2_6
1
2.2/F_6
4
PQ36
AOL1718
*0/short_4
CPU_SVD
CPU_CORE
PL7
0.36uH
8380LX2
<4>
T4
1
PU9
2
PR45
6.2K/F_4
1
PC124
0.1u/25V_4
OCP: 20A
12A
T3
PR2
3.92K/F_4
1
PR3
2_6
16
15 8380BST1
14
13
12
8
10
9
LX1
BST1
LDR1
GNDP
VDDP
HDR2
BST2
LX2
8380RSN2
8380RSP2
8380VFIX
8380CSN2
8380CSP2
8380VIN
PR40
2.55K/F_4
PR173
10K_6_NTC
PR174
PD2
RB501V-40
1
2
3
5
4
6
7
11
35
36
37
GNDA
GNDA
8380VREF
Close to Phase
Inductor
PR161
5
8380SC
8380RSN1
8380RSP1
8380CSN1
8380CSP1
8380EN
PC129
0.22u/6.3V_4
PR39
49.9K/F_4
22
24
23
20
21
19
18
17
38
39
40
42
41
GNDA
GNDA
8380ILIM
PC99
0.22u/25V_6
RSN2
RSP2
VFIX
CSN2
CSP2
VIN
PG
LDR2
GNDA
GNDA
GNDA
8380TSET
COMPV1
VDDA
VREF
TSET
ILIM
SVD
SVC
COMPV2
PR156
2.2/F_4
PC16
PC168
0.1u/50V_6
*10U/25V_1206
PQ32
AOL1448
+5VPCU
SC
RSN1
RSP1
CSN1
CSP1
EN
PWR_OK
HDR1
GNDA
GNDA
GNDA
1
2
25
26
27
28
29
30
31
32
0.1U/50V_6
8380LX1
PC125
470P/50V_4
PC126
1u/6.3V_4
PC112
PC110
100u/25V_6X5.8
4
+5VPCU
C
PC169
4.7U/25V_8
+
5.62K/F_4
8380HDR1
PR1
22_6
PC5
6.8n/25V_4
1
CPU_PWRGD_SVID_REG
PR16
1K/F_4
2
8380VREF
PR28
*49.9K/F_4
T55
3
1
<4>
PR11
10K_4
Parallel
PR20
*0/short_4
T2
VIN
1
8380VREF
D
+3V
1
<4> CPU_VDD_FB_L
8380RSP1
2
SNS_POS_VDD_0
2
PR32
*0/short_4
<4> CPU_VDD_FB_H
2
D
PC7
100p/50V_4
SNS_POS_VDD_1
8380CSP2
8380CSN2
8380RSP2
1
PR17
1.2K/F_4
2
PR15
49.9/0.1%_6
PC109
6.8n/25V_4
PR14
*100K/F_4
CPU_VDDNB_CORE
+3V
PR9
*0/short_6
A
A
Quanta Computer Inc.
PROJECT : ZH9
Size
Document Number
Rev
4A
AMD CPU Core (OZ8380)
Date:
5
4
3
2
Sunday, March 28, 2010
Sheet
1
28
of
40
5
4
3
2
1
VIN
+5VPCU
PR78
10/F_4
D
D
PR81
1M/J_6
PR90
2.2/F_6
PC54
0.1U/25V_4
PR82
*10K/F_4
EN/DEM
16
TON
1
VOUT
2
VDD
3
C
<25> HWPG_NB_CORE
PC50
1U/10V_4
12
UGATE-NB_CORE
PHASE
11
PHASE-NB_CORE
OC
10
LGATE
GND
PGND
7
NC
TPAD
17
6
5
14
NC
5
UGATE
8
PC61
0.1U/50V_6
PC167
4.7U/25V_8
0.95V/7.5A
OCP: 9.5A
3
2
1
13
9
PGOOD
PC58
0.1U/50V_6
BOOT
VDDP
FB
4
PC134
2200P/50V_4
4
PL11
1.0uH/11A_7X7X3
+NB_CORE
5
+3VSUS
15
PC173
*10U/25V_1206
PQ41
FDMC8884
PR85
1/F_6
PU5
UP6111AQDD
PR84
10K/F_4
MAINON
PC60
4.7U/6.3V_6
PR88
6.19K/F_4
PR91
2.2/F_4
PC57
1U/10V_4
C
LGATE-NB_CORE
+
4
Rds*OCP=RILIM*20uA
PQ40
FDMC8296
PC66
2200P/50V_4
3
2
1
<25,30,32> +1.8V_ON
<25,30,32,33>
PD6
RB500V-40
PR202
*10K/F_4
PC69
PC67
PC68
330U/2V_7343 10U/10V_8 0.1U/50V_6
PC52
*1000P/50V_4
TON=3.85p*RTON*Vout/(Vin-0.5)
Frequency=Vout/(Vin*TON)
R1
PR76
2.67K/F_4
PC49
33P/50V_4
NB_CORE_FB
TON=3.85p*1M*1/(Vin-0.5)
+5VPCU
PR75
NB_CORE_FB 13K/F_4
B
3
PR70
10K/F_4
2
Frequency=1/(0.0036767)=272K
PR77
10K/F_4
PQ8
DMN601K-7
PR66
100/J_4
1
R2
Rdson=13mOhm
L(ripple current)
=(19-1)*1/(1u*272k*19)
~3.646A
HI --- 0.95V
LOW ---1.1V
PR69
*0/J_4
PC46
0.01U/25V_4
3
VOUT=(1+R1/R2)*0.75
+NB_CORE_ON
<8>
2
PR79
A
*0/short_6
PQ7
DMN601K-7
A
Quanta Computer Inc.
PR68
*100K/J_4
PROJECT : ZH9
2
1
13m*9.5=RILIM*20uA
RILIM=6.19K
1
Size
Document Number
Rev
4A
NB_CORE(UP6111A)
Date:
Sunday, March 28, 2010
Sheet
1
ho
tm
ai
l.c
om
2
f@
3
in
4
xa
5
he
B
29
of
40
5
4
3
2
1
[PWM]
PC25
4.7U/6.3V_6
PC23
0.1U/50V_6
PR49
1/F_6
<15> +SMDDR_VTERM
VIN
PC27
4.7U/6.3V_6
0.375A
D
1
PC30
4.7U/6.3V_6
5
D
PR186
*2.2/F_4
PQ35
FDMC8884
+
PC159
*2200P/50V_4
DRVL
LL
DRVH
VBST
3
2
1
VTTGND
VLDOIN
VTT
GND
1
PGND
PC151
100u/25V_6X5.8
2
19
20
21
22
23
24
25
4
PC123
2200P/50V_4
PC165
*4.7U/25V_8
PC164
*4.7U/25V_8
1.5V/5.1A
OCP: 7A
+1.5VSUS
18
+1.5VSUS
2.2uH/8A_7X7X3
VTTSNS
CS_GND
17
PL8
5
2
V5IN
15
V5FILT
14
PGOOD
13
MODE
5
VTTREF
6
COMP
16
PR30
9.1K/F_4
2
NC
S5
PR31
*100K/F_4
12
11
S3
VDDQSNS
VDDQSET
9
10
7
PC29
33N/25V_4
8
C
NC
+5VPCU
0.08A
PR33
5.1/F_6
PQ34
FDMC8296
4
+5VPCU
1
<15> +SMDDR_VREF
CS
PR172
2.2/F_4
+
3
2
1
4
GND
1
+1.5VSUS
RT8207A
PU2
PC13
1U/6.3V_4
2
3
PC14
1U/6.3V_4
PC128
2200P/50V_4
PC31
330U/2V_7343
PC32
10U/10V_8
C
+3VPCU
HWPG_1.5V <25>
PR36
620K/F_4
S5_1.8V
S3_1.8V
PR54
*0/J_4
FOR DDR III
PR50
*0/J_4
PR41
*0/short_4
PR48
*0/short_4
VIN
(For RT8207A
SUSON
<25,33>
MAINON
<25,29,32,33>
400KHZ )
S5_1.8V
+5VPCU
S3_1.8V
PR44
*0/J_4
PR55
*0/short_4
<4> CPU_VDDIO_FB_H
PR51
10K/F_4
VOUT=(1+R1/R2)*0.75
R1
Rdson=13mOhm
L(ripple current)
=(19-1.8)*1.8/(2.2u*400k*19)
~1.03A
PR52
10K/F_4
13m*7=RILIM*10uA
RILIM=9.1K
(10u*PR35)/Rdson+Delta_I/2=Iocp
R2
B
VIN_SRC
+1.5V
PR197
*1M/F_4
+1.8V_D
+1.5VSUS
+15V
PR199
22_8
PR200
*1M/F_4
*0/short_6
MAIND
+1.8V_D
<27,33>
4A
2
PR198
1M/F_4
2
1
2
1
1
PQ50
*DTC144EUA
PQ55
DMN601K-7
PQ54
DMN601K-7
PC161
*2.2n/50V_4
+1.5V
0.054A
2
PR196
100K_4
PQ42
AO3404
1
2
<25,29,32> +1.8V_ON
1
3
3
MAIND
3
PR56
B
PR201
0/J_4
MAIND
3
PC26
*33P/50V_4
A
A
1/29 modify for sequence
Quanta Computer Inc.
PROJECT : ZH9
Size
Document Number
Rev
4A
DDR 1.5V(RT8207A)
Date:
5
4
3
2
Sheet
Sunday, March 28, 2010
1
30
of
40
5
4
3
2
1
VIN
PR67
+5VPCU
PR74
10/F_4
*0/short_6
D
D
PR80
1M/J_6
PR87
2.2/F_6
PC53
0.1U/25V_4
PR71
*10K/F_4
C
PR89
1/F_6
<25> HWPG_1.1V
PC48
1U/10V_4
EN/DEM
16
PC63
2200P/50V_4
4
PC62
0.1U/50V_6
PC166
4.7U/25V_8
BOOT
13
TON
UGATE
12
1.1V_DH
1
VOUT
PHASE
11
1.1V_LX
2
VDD
OC
10
3
FB
4
PGOOD
6
5
14
NC
VDDP
9
LGATE
8
GND
PGND
7
NC
TPAD
17
1.1V/7.3A
OCP: 8.5A
3
2
1
PC59
0.1U/50V_6
PL9
1.0uH/11A_7X7X3
5
+3VSUS
15
PC174
*10U/25V_1206
PQ38
FDMC8884
PR86
5.49K/F_4
+1.1V_S5
PR176
2.2/F_4
PC56
1U/10V_4
C
+
1.1V_DL
4
Rds*OCP=RILIM*20uA
PQ39
FDMC8296
PC135
2200P/50V_4
3
2
1
<25,27,34> S5_ON
PC55
4.7U/6.3V_6
PU4
UP6111AQDD
PR83
10K/F_4
5
PD7
RB500V-40
PC145
PC71
PC70
330U/2V_7343 10U/10V_8 0.1U/50V_6
PC51
*1000P/50V_4
PR65
*0/short_4
B
B
+1.1V_S5
SUSD
MAIND
<27,30,33>
SUSD
<27,33>
PR72
4.7K/F_4
R2
PR73
10K/F_4
PC47
33P/50V_4
3
MAIND
R1
1.1V_FB
SUSD
4A
2
PQ37
AO3404
1
VOUT=(1+R1/R2)*0.75
TON=3.85p*RTON*Vout/(Vin-0.5)
13m*8.5=RILIM*20uA
RILIM=5.49K
PROJECT : ZH9
Size
Sunday, March 28, 2010
Sheet
1
tm
ai
l.c
om
2
ho
3
f@
4
Rev
4A
VCCP 1.1V(UP6111A)
Date:
5
Document Number
in
Frequency=1/(0.0036767)=272K
A
Quanta Computer Inc.
xa
TON=3.85p*1M*1/(Vin-0.5)
0.6A
he
Frequency=Vout/(Vin*TON)
A
+1.1VSUS
Rdson=13mOhm
L(ripple current)
=(19-1.1)*1.1/(1u*272k*19)
~3.81A
31
of
40
5
4
3
2
1
D
D
+3VPCU
1.8V/1.418A
OCP: 6A
+1.8V
PC140
0.1U/25V_4
PC141
10U/10V_8
PU11
16
1
PR178
0/J_4
2
+1.8V_EN
54418_VFB
PC139
1000P/50V_4
PR183
5.49K/F_4
MAINON
PR184
182K/F_4
PC143
*100P/50V_4
15
PH
VIN
PH
VIN
PH
10
12
BOOT
13
6
VSNS
PWRGD
14
7
COMP
GND
3
8
RT/CLK
GND
4
9
SS
AGND
5
EN
C
PL10
3.3uH/6A_7X7X3
11
PR177
1/F_6
PC138
0.1U/50V_6
HWPG_1.8V <25,33>
PR179
*10K/J_4
PC142
0.1U/25V_4
+3VSUS
22
21
20
19
18
17
MAINON
HPA00835RTER
VIN
PAD
PAD
PAD
PAD
PAD
PAD
C
MAINON <25,29,30,33>
PC148
10U/10V_8
PC146
10U/10V_8
PR181
100K/F_4
PC144
0.01U/25V_4
R1
54418_VFB
PC147
4700P/25V_4
PR182
78.7K/F_4
+3V
R2
B
B
PR187
*0/J_4
V0=0.8*(R1+R2)/R2
+1.8V_EN
<25,29,30> +1.8V_ON
PR189
*0/J_4
PR188
*0/J_4
1/29 modify for sequence
A
A
Quanta Computer Inc.
PROJECT : ZH9
Size
Document Number
Rev
4A
+1.8V(TPS54418)
Date:
5
4
3
2
Sunday, March 28, 2010
Sheet
1
32
of
40
5
4
3
2
1
+1.1V_S5
+1.1V
PR192
22_8
PR193
*1M/F_4
D
5
6
7
8
PR191
*1M/F_4
+15V
PR194
1M/F_4
1
PQ48
AO4468
3
2
2
PQ53
DMN601K-7
1
PQ56
*DMN601K-7
1
PR195
100K_4
D
4
PC160
*2.2n/50V_4
PQ52
DMN601K-7
1
2
<25,32> HWPG_1.8V
+3V
3
3
+1.1V_D
3
2
1
VIN_SRC
CPU_VDDR_FB_H <4>
+1.1V
2
PR57
100K/F_4
+5VPCU
PU3
RT9025-25PSP
<25,28> VRON
4
VEN
3
8
9
VIN
GND
GND
PC33
10u/10V_8
C
PC35
0.1u/50V_6
1
VO
6
NC
5
7
+1.5VSUS
VPP PGOOD
2
ADJ
PC20
0.1u/50V_6
PR58
*0/short_4
2
1
PC34
*0.1u/50V_6
5.78A
1/25 modify for sequence
PR175
*0/J_4
HWPG_VDDR <25>
MAIND
+1.1V_D
CPU_VDDR
PC21
10u/10V_8
0.8V
1.2VADJ0.9V
PR190
0/J_4
0.75A
PR35
4.02K/F_6
PR43
30.1K/F_6
PR42
*22.1K/F_4
C
Vout =0.8(1+R1/R2)
=0.9V
3
PQ2
*DMN601K-7
PR53
<10> VDDR_OPT
*33_4
2
1
PC28
*220P/50V_4
2.5V/0.188A
PU10
MAINON
3
PR180
*0/short_4
2
+3VPCU
PC137
2.2U/6.3V_6
1
SHDN
VO
5
+2.5V
GND
VIN
NC
+ PC132
4
PC133
10U/10V_8
G9091-250
*100U/6.3V_3528
PC136
*0.1U/25V_4
VIN_SRC
+3VSUS
B
PR142
1M/J_6
+1.1VSUS
PR145
22/J_8
+15V
B
PR140
1M/J_6
PR144
22/J_8
3
3
<27,31>
3
3
SUSD
SUS_ON_G
2
2
2
VIN_SRC
+3V
PR103
1M/J_6
PQ25
DMN601K-7
+5V
PR97
22/J_8
PC91
*2200P/50V_4
1
PQ26
DMN601K-7
1
PQ27
DMN601K-7
1
PQ28
DTC144EU
1
PR148
100K/J_4
+1.1V
PR98
22/J_8
+1.5V
PR99
22/J_8
+15V
PR118
22/J_8
PR116
1M/J_6
MAINON_ON_G
MAIND
MAIND
3
3
3
3
<27,30>
tm
2
ho
PC84
*2200P/50V_4
f@
PQ19
DMN601K-7
Date:
5
4
3
2
Quanta Computer Inc.
PROJECT : ZH9
Document Number
he
Size
in
1
PQ18
DMN601K-7
xa
2
PQ15
DMN601K-7
1
2
PQ14
DMN601K-7
1
1
PR96
100K/J_4
2
PQ13
DMN601K-7
1
PQ11
DTC144EU
2
1
PR104
1M/J_6
2
<25,29,30,32> MAINON
A
ai
3
3
A
l.c
om
PR147
1M/J_6
2
<25,30> SUSON
Rev
4A
Discharge (2.5V/1.2V/VDDR)
Sheet
Sunday, March 28, 2010
1
33
of
40
1
2
3
4
5
VIN
A
A
PD9
SW1010CPT
1
PR100
1M/F_4
PQ10
AO3409
3
TSNS_ON 2
S5_ON
3
2
Thermal protection
VL
B
1
PQ12
DTC144EU
VL
B
SYS_SHDN# <4,27>
PR108
200K/F_4
3
+
2
-
1
3
2.469V
2
PQ16
DMN601K-7
4
PU6A
LM393
PC81
0.1U/25V_4
1
PR110
10K/J(NTC) _6
<25,27,31> S5_ON
PR92
200K/F_4
8
PC72
0.1U/25V_4
3
PR107
1.74K/F_4
2
PR109
200K/F_4
PQ17
DMN601K-7
C
1
C
+3VPCU
VL
PR93
100K/F_4
PR94
10K/F_4
PU6B
5
4.95V
6
+
PD8
7
T51
RB500V-40
LM393
For EC control thermal protection (output 3.3V)
PR95
1M/F_4
D
D
Quanta Computer Inc.
PROJECT : ZH9
Size
Document Number
Rev
4A
Thermal protect
Date:
1
2
3
4
Sunday, March 28, 2010
Sheet
5
34
of
40
5
4
3
2
1
INTERNAL CLOCK MODE
D
D
EC Page 25
Debug card
HD AUDIO
Page 19
SPM_CLK
800MHz
RTC_CLK
33MHz
C
PCIE_PE0_CLKP/N
100MHz
PCIE_PE1_CLKP/N
100MHz
PCIE_LAN_CLKP/N
100MHz
AMD SB820
INT CLK MODE
LPC_CLK0
33MHz
AZ_BIT_CLK
24MHz
SIDE PORT MEMORY CHIP
Page 6
NB_REFCLK_P/N
100MHz
A-LINK
100MHz
C
AMD NORTHBRIDGE
RS880M
Page 6~9
100MHz
AMD
ASB2 CPU
Page 2~5
HT_REFCLKP/N
100MHz
800MHz
NB_GFX_REFCLKP/N
M_A_CLKP/N
CPU_CLKP/N
200MHz
A SO-DIMM
Page 15
MINICARD-WLAN Page 23
MINICARD-3G
Page 23
LAN-AR8152
Page 21
Page 10
B
B
For MASTER
(25MHz)
For RTC
(32.768KHz)
For SATA
(25MHz)-DNI
A
A
Quanta Computer Inc.
l.c
om
PROJECT : ZH9
Size
Document Number
Rev
4A
Date:
Sunday, March 28, 2010
f@
ho
tm
2
in
3
xa
4
he
5
ai
Clock Distribution Diagram
Sheet
1
35
of
40
5
4
3
CPU_CORE@20A
<0.7V-1.1V,12A>
CPU core
(OZ8380)
PU?
POWER
VIN
CPU_VDDNB_CORE@3A
<0.9V,1.5A>
VIN
[email protected]
<0.95V~1.1V,6A>
1
Distribution
LCD Backlight, CPU_CORE,NB_CORE, +5VPCU, +3VPCU, +1.5VSUS, +1.1V_S5
CPU_CORE
NorthBridge
(uP6111AQDD)
PU?
2
CPU_VDDNB_CORE
CPU
power supply for on-die NorthBridge
NorthBridge power supply
NB_CORE
D
D
+5VPCU
USB Connecter
+5VPCU
+5VPCU
<AC/DC Insert>
CRT,Touch Pad ,Audio codec,SATA
+5V
+1.8V
AO3404
PQ??
+5V
<MAIND>
+3VPCU
<AC/DC Insert>
NB & SB power supply
+3VPCU
RTC, Hall Sensor, System LED, EC, BIOS, Acer ID EEPROM, +3V_S5, +3VSUS, +3V
+3V_S5
SouthBridge,LAN , LAN EEPROM , RJ45 LED
+3VSUS
3G
VIN
+3V
SYSTEM
5V/3V
(RT8206B)
AO3404
PQ?
+3V_S5
<S5D>
CLK_GEN, CPU, NB,SB, LCD power switch,CCD, DMIC, BT, System LED, Codec, WLAN/Wimax, Card reader, EC
+2.5V
CPU,Discharge
CPU,DDR,Discharge
+1.5VSUS
+3VPCU
PU?
C
AO3404
PQ?
+3VSUS
<SUSD>
CPU,DDR,NB
+SMDDR_VTERM
AO3404
+3V
<MAIND>
PQ?
ADAPTER
+SMDDR_VREF
+1.1V_S5
CHARGER
BATTERY
+1.5V
G909-150T1U
PU?
VIN
ISL88731HRZ-T
PU?
+2.5V
<MAINON>
+1.1VSUS
+1.1V
HPA00835RTER
PU?
+1.8V
<MAINON>
CPU_VDDR
DDR
C
CPU, DDR
NorthBridge,Discharge
Southbridge
CLK_GEN,CPU,NB,SB
CPU
BOM Structure
VIN
+1.5VSUS
+1.5VSUS
<SUSD>
B
DDR PWR
1.5V
RT8207A
AO3404
PQ?
+1.5V
<MAIND>
RT9025-25PSP
PU?
PU?
CPU_VDDR
<VRON>
Fun.
Description
SPM@
w/ Sideport RAM
3G@
w/ 3G module
BT@
w/ BT module
HDM@
w/ HDMI
BOM@
BOM Control
B
[email protected]
<[email protected]>
[email protected]
<[email protected]>
SB Core logic
standby power
UP6111AQDD
PU?
[email protected]
<1.1V,7.3A>
+1.1V_S5
A
AO4468
PQ?
+1.1V
<MAIND>
AO3404
PQ?
+1.1VSUS
<SUSD>
A
Quanta Computer Inc.
PROJECT : ZH9
Size
Document Number
Date:
Sunday, March 28, 2010
Rev
4A
Power Tree
5
4
3
2
1
Sheet
36
of
40
5
4
3
2
Nile Power On Sequence
VCCRTC
VIN
+5VPCU +3VPCU
From PWM to EC HWPG_SYS
From Button to EC NBSWON#
From EC to PWM S5_ON
From VBAT
From AC,BATT
D
EC_RSMRST# not de-asserted until at least 10 ms after S5_3.3V is valid.
+3.3V_S5
+1.1V_S5
HWPG_1.1V
EC_RSMRST#
DNBSWON#
From PWM to EC
From EC to SB
From EC to SB
From SB to EC
From EC to PWM
100ms(EC define)
SUSC#,SUSB#
SUSON
+3.3VSUS
MAINON
+5V/3.3V
+1.8V
From PWM to EC HWPG_1.8V
+2.5V
+1.5V
C
SB_PWRGD(ECPWROK) de-asserted at least 80 ns before VDDCR_11(+1.1V) drops 5% from nominal value.
+1.1V
+NB_CORE
HWPG_NB_CORE
VRON
From EC to PWM
GROUP B
+1.1VSUS
HWPG_1.5V(SUS)
From EC to PWM
GROUP A
C
RC=~22ms , CPU_VDDNB_CORE should not ramp before 1.1V
CPU_VDDNB_CORE
CPU_CORE
CPU_COREPG
CPU_VDDR
HWPG_VDDR
+1.1V_CPU_VLDT
From PWM to EC,SB
From PWM to EC
D
RS880:
1.+1.1V valid before NB_PWRGD HIGH >= 1 ms
2.+1.8V_NB_IOPLLVDD18c(+1.8V) cannot ramp before the 3.3-V rails
3.+1.5V_SPM_VDDQ(+1.5V)cannot ramp before the 3.3-V rails
4.+1.8V_NB_VDDLTP18(+1.8V)cannot ramp before the 3.3-V rails
5.+1.8V_NB_PLLVDD18(1.8V)cannot ramp before the 3.3-V rails
6.3.3-V rails cannot exceed the 1.8/1.5-V Sideport or 1.8-V Display
and PLL rails by > 2.1 V.
7.IOPLLVDD/PLLVDD(+1.1V) cannot ramp up before the 1.8/1.5-V Sideport
or 1.8-V Display and PLL rails.
8.VDDC(+NB_CORE) rail cannot ramp before the 1.1-V PLL rails.
CPU_VDDIO_SUS(+1.5VSUS)
MEM_VTT,MEM_VREF
From PWM to EC
1
Power on sequence required:
SB820:
1.EC_RSMRST# ramp up time (10% to 90%) <= 50 ms
2.SB_PWRGD(ECPWROK) rise time <= 50 ms
3.SB_PWRGD(ECPWROK) fail time <= 1 ms
4.SB_PWRGD(ECPWROK) de-asserted at least 1 ns before EC_RSMRST# is
asserted when entering G3 state.
5.VBAT will be valid at least 5 seconds before S5_3.3V and S5_1.1V are
ramped up to allow start time for internal RTC.
6.50us<=all power rails rise time except +3.3V_S5<=40ms
7.100us<=+3.3V_S5 rise time<=40ms
8.+1.8V_S0 rails cannot ramp before the +3.3V_S0 rails.
9.+1.1V_S0 rails cannot ramp before the +1.8V_S0 rails.
10.+1.1V_S0 rails cannot ramp before the +3.3V_S0 rails.
11.+1.1V_S5 rails cannot ramp before the +3.3V_S5 rails.
12.+3V_S5 ramp down time > 300 µs.
RC=~4.7ms
SB_PWRGD rise time<50ms
From EC to SB SB_PWRGD(ECPWROK)
From SB to NB NB_PWRGD,NB_PWRGD_IN
SB_PWRGD to NB_PWRGD:22~500ms
HT REFCLKP/N ramp before NB_PWRGD >= 1 ms.
>1ms
HT_REFCLKP/N(NB INPUT CLK)
CPU_CLKP/N ramp before CPU_PWRGD >= 1 ms.
>1ms
CPU_CLKP/N(CPU INPUT CLK)
B
B
From SB to CPU CPU_PWRGD
From SB to NB NB_RST#_IN
From SB to CPU CPU_LDT_RST#
A_RST# to PCI_RST#<100ns
SB_PWRGD to A_RST#:101~113ms
>1ms
>1ms
SB SMBUS Table
EC SMBUS Table
A
A
MOS CKT (Level shift)
X
X
EC775 SDA1 / SCL1 (+3VPCU)
V
V
EC775 SDA2 / SCL2 (+3V)
EC775 SDA3 / SCL3 ()
Power Plane
X*
MOS CKT (Level shift)
*Reserve: There is not SMBUS function in AVL
ai
V
+3V
tm
V
+3V
+3VPCU
+3V
X
X
ho
V
+3V
CPU thermal Sensor
f@
Power Plane
Battery
Mini Card (WLAN)
in
(SB_DA0)/(SB_CL0) (+3V)
RAM
Quanta Computer Inc.
xa
CLK GEN
Document Number
Date:
Sunday, March 28, 2010
he
PROJECT : ZH9
Size
Rev
4A
POWER SEQUENCE
5
4
3
l.c
om
Notice:
1.CPU_LDT_RST# msut be asserted a minimum of 1ms prior to the assertion of CPU_PWRGD
2.CPU_CLKP/N must be within specification a minimum of 1ms prior to the assertion of CPU_PWRGD
3.CPU_PWRGD remains deasserted at least 1ms after both CPU_CLKP/N and all voltages to the processor are within specification for operation
4.all NB power rails(1.8V/1.2V/1.1V) valid before NB_PWRGD at least 1ms
5.stable input clocks from CLKGEN(HT_REFCLKP/N) to NB before NB_PWRGD at least 1ms
2
1
Sheet
37
of
40
5
4
3
SLP_S3#(SUSB#):
S3 Sleep Power plane control Assertion of SLP_S3# shuts off power to non-critical components
when system transitions to S3, S4, or S5 states.
2
NBSWON#
5
SLP_S5#(SUSC#):
S5 Sleep Power plane control - Assertion of SLP_S5# shuts power off to non-critical components
when system transitions to S4 or S5 state.
4
+3VPCU
S5_ON
PQ?
BATT Charger
PU?
D
VIN
+VIN
Regulator
+3VPCU
+1.1V_S5
PU?
Always System power
Regulator
PU?
Battery
+3V_S5
MOS
1b
1
AC Adapter
1
3
6
7
+5VPCU
EC_RSMRST#
10
8
DNBSWON#
2
SUSON
D
RSMRST#
26
CPU_LDT_RST#
PWRBTN#
LDT_RST#
13
SUSC#
9
SLP_S5#
MAINON
EC
SUSB#
SLP_S3#
17
RESET_L
VRON
SB820
22
ECPWROK(SB_PWRGD)
ASB2
SB_PWRGD
CPU_VDDNB_CORE
VIN
Regulator
PU?
U7
24
18
CPU_CORE
LDT_PG
A_RST#
CPU_PWRGD
PWROK
C
C
19
CPU_COREPG
+5VPCU
CPU_VDDR
20
Regulator
PU?
+VIN
Regulator
PU?
U11
+NB_CORE
HWPG_SYS
16
+1.1V_S5
MOS
+1.1V
NB_PWRGD
NB_RST#_IN
HWPG_NB_CORE
14
PQ?
B
23
25
CPU_COREPG
HWPG_VDDR
21
PWRGOOD
14
+2.5V
+3VPCU
LDO
PU?
HWPG_1.1V
6
HWPG
B
HWPG_1.8V
SYSTEMSETb
HWPG_1.5V
RS880
+3VPCU
Regulator
PU?
+1.8V 15
14
+3VPCU/+5VPCU
+3V
MOS
+5V
U9
PQ?
+1.1V_S5
MOS
+1.1VSUS
PQ?
12
+1.5V
A
VIN
Regulator
PU?
14
A
MOS
+1.5VSUS
PQ25
+SMDDR_VTERM
+SMDDR_VREF
11
+3VPCU
+3VSUS
MOS
Quanta Computer Inc.
PROJECT : ZH9
PQ?
Size
Document Number
Rev
4A
power sequence block diagram
Date:
5
4
3
2
Sunday, March 28, 2010
1
Sheet
38
of
40