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X Workshop ATLAS Italia
10 – 12 February 2015
G. Darbo – INFN / Genova
Indico:
https://agenda.infn.it/conferenceDisplay.py?confId=8955
G. Darbo – INFN / Genova
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Inner Tracker Project
ATLAS ITk project taking off:
• Project kick-off meeting (4 Nov ‘14) chaired by Leo;
• 93 Institutes and 21 countries joined ITk;
• 6 Italian Institutes already in ATLAS (BO, CS,GE, LE,
MI, UD) – Trento asked to join ATLAS and then ITk.
ITk Institute Board (IB)
Trento raised formal
request to join ATLAS
• Under Leo, the search committee to find the first
chair of the ITk-IB has been formed: C Buttar,
Marina Cobal, Abe Seiden (chair), Nobu Unno,
Norbert Wermes and Dave Charlton  hope new
chair for first IB meeting.
• First ITk-IB meeting (26th Feb) in ITk-week, where we
will discuss various items including the effort tables
collated by Leo and a discussion of the critical gaps
in coverage for certain areas.
G.Darbo – INFN / Genova
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Country
Number of institutions
Australia
3
Canada
7
CERN
1
China
1 (cluster)
Czech Republic
3
Denmark
1
France
6
Germany
10
Italy
6: BO, CS, GE, LE, MI, UD
Japan
7
Netherland
1
Norway
2
Poland
2
Russia
1
Switzerland
2
Spain
2
Slovenia
1
Sweden
2
South Africa
1 (cluster)
Taiwan
1
United Kingdom
12
United States
21
Total
93
Milano, 10 February 2015
2
ITk Descoping Scenario
• LHCC request a cost document for ATLAS Phase II with possible descoping – document ready for discussion on 15th Sep, draft to
LHCC for June.
• ATLAS mandate a subgroup of the USC to study 3 scenarios: 275,
235 and 200 MCHF (old CHF rate!).
• For ITk too short time to focus on “preferred” layout (many under
study  see Layout TF).
• Concentrate on LoI layout + extension at h = 4
• For ITk should be considered as pure exercise: not what we are going to build,
but how performance goes with de-scoping
• Effort must be coherent with CMS
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ITk “275” layout
• LoI + VF extension to h = 4
• Not clear if we can simulate rings in
time (presumably not…)
• Should be possible to move to 25x100
pixel size (occupancy/rates)
Cost
Strips
95.7 M
Pixel
24.8 M
Common
11.0 M
VF extension
12.0 M
Savings (wrt LoI)
-8.7 M
–––––––––––––––––––––––––
Total
134.8 M
Ref.: P. Morettini – R&D Phase II Italia – 23/1/2015
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ITk “235” layout
Cost
WRT “275”:
• VF extension only to h=3.2
• Strip “stub” layer removed
“275”
134.8 M
VF to h=3.2
-6.0 M
Stub
-2.0 M
–––––––––––––––––––––––––
Total
126.8 M
Ref.: P. Morettini – R&D Phase II Italia – 23/1/2015
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ITk “200” layout
WRT “275”:
• VF extension only to h=3.2
• 1 strip barrel and 1 disk set removed
• 2 strip barrel single layer (not stereo)
Cost
“275”
134.8 M
VF to h = 3.2
-6.0 M
1 barrel+1disk
-24.0 M
2 barrel layers
-7.0 M
–––––––––––––––––––––––––
Total
97.8 M
Ref.: P. Morettini – R&D Phase II Italia – 23/1/2015
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ITk Layout tasks force
• New Task Force (Claudia e Andy chairs), with mandate to define
the ITk layout  go down in options, by end 2015.
• Need help for simulation (interesting task for young people too).
To study:
Layout TF Work Model
 Local supports for layers 3-4
(inclined planes, like “alpine”
 less silicon and material)
 Look at extra pixel layer(s) with
cheaper technologies to replace
strips.
 Realistic simulation of services
and routings.
 R/O sizing based on detector
characteristics.
Ref.: P. Morettini – R&D Phase II Italia – 23/1/2015
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SLIM – Stiff Longeron for ITk Staves
IP
Barrel Cells
Tilted Cells
5th pixel layer inside the PST –
HV-CMOS “optimized” – 2.5 m
long at layer 5.
one slim stave is equivalent to two
adjacent conventional staves
Connecting Structure
G.Darbo – INFN / Genova
Ref.: S. Michal, ITk Pixel Design Group, 29/01/2015
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SLIM – Material Budget
2.5m FULL BARREL vs TILTED SLIM
Lower surface and consequently lower cost
22 % less for a 1.5 m stave at layer 5
39 % less for a 2.5 m stave at layer 5
• Only
the structural
cells are studied
Note:
only structural
cells studied
• The longer the stave, the better it is
4.00
BARREL vs TILTED 2.5 m
3.50
3.00
Barrel to tilted cell
%X/X0
2.50
2.00
1.50
1.00
8 per. Mov. Avg. (TILTED DET SLIM MOY TOT %X/X0
PER DEGREE)
8 per. Mov. Avg. (BARREL DET SLIM MOY TOT %X/X0
PER DEGREE)
0.50
0.00
0.0
0.5
Sébastien MICHAL
G.Darbo – INFN / Genova
1.0
Eta
1.5
2.0
Slide 33
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2.5
Ref.: S. Michal, ITk Pixel Design Group, 29/01/2015
Milano, 10 February
January,
27th 2015
20149
Tracker R&D in CSN1
RD_FASE2
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• Test structures show good breakdown behaviour.
• Defect rate higher than IBL (DRIE process, partially understood),
no totally good FE-I4!
• One wafer will be bump-bonded at IZM/Selex with special
bump-mask: leave unconnected pixel column with low VBD
• Planning irradiation & test-beam with FE-I4/PSI46dig
ATLAS FE-I4 (13x)
Passing-through ohmic columns
Partially etched junction columns
Column (10÷13 µm) partially filled with
doped poly-silicon
CMS Single chip (24x)
(1E, 2E, 3E, 4E)
CMS Quads (6x)
(2E, 3E)
275 µm
• 1st 3D test batch on 6” wafers finished, all wafers tested.
250µm
IBL like 3D sensor on 6” – FBK and Trento
Process x-section
3D Sensors with FBK: TN + FBK
One FE-I4 tile: IV for 80 cols of 336 pixels
Bad IV Pixel columns:
disconnect from Pixel inputs
MEDIPIX2 (4x)
NA62 test chip (20x)
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Good IV Pixel columns:
BB to FE-I4 pixel
Ref.: G. Giacomini – R&D Phase II Italia
Milano, 10 February 2015
11
3D / Active Edge – RD_FASE2
Batch 1 – mechanical test
• DRIE test of 100 ÷ 150 µm
narrow (5 µm) columns;
• Test filling with poly.
G.Darbo – INFN / Genova
n++ col
Bump-bond
p++
Charge Amp.
P- Epi layer /
P- High Ω•cm wafer
P++ Low Ω•cm wafer
100÷130µm
Opt.: 200 nm
oxide (SOI)
Thin-down
col
-Vb
metal
3.8 um
158 um
• Single-sided process on SiSi
DWB and SOI substrates –
Substrates from IceMOS;
• 100÷130 µm thick active layer;
• Technology suitable for new
RD53 Pixel chips (small 50x50 or
25x100 µm2 pixels) and low
threshold (~1000 e-) operation;
• Design for 2x1016 neq/cm2;
• Strategy: 3 technical batches
funded by CSN1 (ATLAS/CMS) +
[1 batch of Active edge planar
sensors]
Single side 3D process
SOI – SiSi DWB
New generation of 3D sensors
DRIE for ohmic columns
5.6 um
Ref.: M. Boscardin and S. Ronchin, FBK
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Milano, 10 February 2015
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ATLAS - FEI
3D / Active Edge – RD_FASE2
Batch 2 – substrates test
•
•
•
•
•
ATLAS
p-type SiSi DWB wafers from IceMOS
100 ÷ 130 µm high-R active sensor thickness FE-I4
p-spray & p-stop isolation
F2N
Started in Sept. 2014, completed in Nov. 2014
F3N
Good electrical characteristics – from CV
measurements depletion is in accordance with
F5N
nominal thickness of active (device) substrate.
F10N
CMS
FA5S2
FA5S1
F2S
F3S
F5S
F10S
Module assembly:
• 5 wafers will be processed by IZM:
 Substrate thinning
 Metallisation with mask of back
 BCB processing for HV isolation
• 1 wafer bump-bonded by Selex
Table: good tiles per wafers:
• ATLAS (1) – Current limit 0.2 µA, VBD ≥ 100V
• CMS (2) – Current limit 50 nA, VBD ≥ 100V
G.Darbo – INFN / Genova
wafer #
material
thickness
p-spray
ATLAS
(1)
CMS
(2)
30
Si-Si
100
2.00E+12
9 / 10
20 / 30
33
Si-Si
100
2.00E+12
8 / 10
17 / 30
49
Si-Si
100
2.00E+12
8 / 10
20 / 30
63
Si-Si
130
2.50E+12
7 / 10
25 / 30
69
Si-Si
130
2.50E+12
10 / 10
26 / 30
74
Si-Si
130
2.00E+12
8 / 10
19 / 30
75
Si-Si
130
2.00E+12
7 / 10
14 / 30
80
Si-Si
130
1.50E+12
10 / 10
26 / 30
81
Si-Si
130
1.50E+12
8 / 10
26 / 30
1
FZ
275
2.00E+12
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3D / Active Edge – RD_FASE2
2x50 + 2x450
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450 fF
450 fF
50 fF
50 µm
450 µm
• Test small pixels cells with FE-I4 – tricky
layout mixing small pixels and
grounded/larger pixels (see example)
• Wafer layout and cell simulation in advanced
stage – parameters extracted from batch 1
and 2 will be used for the new design
• About 2 month delay accumulated since start
of the project: some concern with the DRIE
machine at FBK (14 weeks asked for repair) –
becoming difficult to have process finished
before summer.
• Substrates
• IceMOS SiSi substrates (baseline option):
already in house
• Shinetsu epitaxial substrates: given-up (not
fulfilling specifications)
• SOI substrates: we are going to order some
wafers (could be used given delay of DRIE).
450 µm
Batch 3 – 3D with new substrates
4x50 + grid
Milano, 10 February 2015
14
Thinking Towards ITk Modules
Assume ITk layer 1 & 2 with 3D
• Need 3000 RD53 chips/single tile sensors to cover the ~1 m2 area.
• Considering 25 tiles/wafer (6”), 50 % yield in sensors and 50 % in good tiles to
used modules: 600 wafers are needed
• FBK + CNM (maybe SINTEF) are in the business – pre-production + production
from 2018 to 2021.
• Requested exercise: evaluate feasibility and cost!
Considerations on bump-bonding
• Complete qualification at Selex with 6” sensor wafers, FE-I4 like modules;
• Discuss with Selex plans for R&D and involvement in ITk production:
 R&D/Upgrade needs at Selex: qualify process for 120k bumps/chip, upgrade to
12” wafers (RD53 wafers).
 Consider 8.2 m2 of hybrid pixels  is Selex interested in part of it?
• Direct playing with FBK and Selex make easier optimization of BB for 3D sensor
and “sell” the full package to the collaboration.
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Steering R/O R&D Activities
Table-top ROD/BOC version (BO)
•
•
•
•
Use expertise on IBL ROD, no VME needs
Full SW/FW compatibility with PIT cards
Half ROD, up to 16 FE
Funded by CSN1
Possible activities on read-out
• Expand existing FE-I4 R/O systems to
HV/HR-CMOS (see bottom fig.)
• Common HW/FW/SW interface definition
• Integrate mini-DCS in the read-out
• GBT concentrator
Generic R/O system
USBPix
RCE
ROD/BOC
PCIExpress
Mod TX/RX
RX
FPGA
TX
LV
CTRL
FE
Ref.: P. Morettini – R&D Phase II Italia – 23/1/2015
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Evaporative CO2 cooling Milano
TRACI
2014 Activities
• Completed design of TRACI v.3



100 W transportable CO2 recirculating system
Collaboration: CERN, NIKHEF, MILANO, SHEFFIELD,
OXFORD, LIVERPOOL
Test on M PUMPS, Corbola (RO)
• Purchased all components:


Being part of collaboration allows purchase sharing
In Milano co-funded by LHCb and Dotazioni
2015 Plans
• Assemble and Commissioning TRACI
• Needed for LHCb and for ATLAS
• Finite Element Analysis of stave designs based on
mini-piping – well known expertise of the MI group
from IBL

Ti pipe, 𝜙 2 mm
Thermal simulation (IBL)
• Test of prototypes with TRACI
 Need to build a setup based on TRACI,
similar to what done for IBL
Test setup
(IBL)
17
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RD_FASE2 – “Richieste 2015”
Attività Descrizione
3D
BB
BO
CS
GE
MI
TN
UD
6" Wafer procurement (SOI, wafer bonding, epi)
-
-
-
-
10.0
-
PicoScope 6407 Digitizer with 1.5 GHz probes and
accessories.
-
-
-
-
8.5
-
6" dummy wafers - test deposition on 6" and
high-density bumps (150 k-bumps/chip)
-
-
-
20.0
-
-
BB for 3D sensor test
-
-
24.0
-
-
-
Upgarde R/O Systems
-
2.0
2.0
2.0
-
2.0
Module assembly and irradiation, RD on flex
-
-
10.0
-
-
-
15.0
-
-
-
-
-
-
-
-
10.0
-
-
15.0
2.0
36.0
32.0
18.5
2.0
MOD
MM-R/O Multi module R/O
CO2/µCH Develop µ-channel cooling
Total requested by ATLAS
105.5
Trento:
Legend:
• Request of 4 k€ of Travel Money
for test-beam participation and
support.
ATLAS
Common ATLAS / CMS
G.Darbo – INFN / Genova
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Activities on HV/HR-CMOS in CSN5 – BO, GE, MI
HVR_CCPD
G.Darbo – INFN / Genova
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HVR_CCPD: The project
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STM Chip
G.Darbo – INFN / Genova
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Hybridization
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AIDA-2020 : Funded !
AIDA-2020 Funded !
• AIDA-2020 has been officially selected by the
EC with a funding of 10 M€.
The project has a ranking of 14.5/15 with
• 5/5 excellence
• 5/5 impact
• 4.5 implementation
INFRAIA-1-2014-2015
The grant agreement
procedure is quite fast
Groups in ATLAS who have
been funded:
• Genova
• Milano
• Trento
Joint Research
AIDA-2020
Figure 3.1: Work Package structure and interactions (Pert chart)
WP1-MGT Project management and coordination
WP15-JRA3
Upgrade of beam and
irradiation test
infrastructure
WP13-JRA1
Innovative gas
detectors
WP10-TA1
Beam test facilities
WP11-TA2
Irradiation test
facilities
Networking
WP5-NA4
Data acquisition system for
beam tests
WP14-JRA2
Infrastructure for
advanced
calorimeters
WP12-TA3
Detector
characterisation
facilities
WP7-NA6
Advanced hybrid
pixel detectors
WP3-NA2
Advanced software
WP4-NA3
Microelectronics and
interconnections
Transnational
Access
WP6-NA5
Novel high voltage and
resistive CMOS sensors
WP9-NA8
New support structures and
micro-channel cooling
WP8-NA7
Large scale cryogenic liquid
detector
WP2-NA1 Innovation and outreach
25
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Conclusions
ITk project moving ahead:
• Kick-off meeting, Institute Board, …
• De-scoping scenarios under study
• Layout TF
RD_FASE2
• Activities on sensors/modules progressing… constructive activity with CMS
HVR_CCPD
• Test chip submitted with STM
• Hybridization work progressing, few devices assembled at Genova tested in TB
AIDA2020
• Project approved, new resources and R&D framework for HL-LHC developments
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SPARE SLIDES
G.Darbo – INFN / Genova
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Activities in ITk
ITk management looking
at interest of Countries in
ITk R&D’s
Italy
Bologna
Genoa
Table from discussion
with Paolo. Comments?
Cosenza
For discussion
Lecce
Milan
Udine
Trento
G.Darbo – INFN / Genova
PIX
PIX
PIX
PIX
PIX
PIX
PIX
PIX
PIX
PIX
HV-HR CMOS sensors
Off-detector DAQ
Simulation
3D sensor development
HV-HR CMOS sensors
Hybridization
Module development, construction and
testing
Local/Global support design
Off-detector DAQ
Simulation
PIX 3D sensor development
PIX Simulation
PIX Simulation
PIX HV-HR CMOS sensors
PIX 3D sensor development
PIX RD53
PIX Hybridization
PIX Module development and testing
PIX Local/Global support design and production
PIX Off-detector electronics (LV power supplies)
PIX Simulation
COM Off-line software
PIX 3D sensor development
PIX Module development and testing
PIX On-line monitoring
PIX 3D sensor development
PIX HV-HR CMOS sensors
PIX Module development and testing
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