Florence
KTH, Stockholm
Trieste
Rome
CNR, Florence
Siegen
Data Acquisition System of the
PAMELA Experiment
Alessandro Basili
INFN Roma II, Università di Roma “Tor Vergata”
Naples
Presentation Overview
1) The acquisition strategy:
system requirements and constraints
data reduction solution
trigger-busy mechanism
2) System details:
Interface Data Acquisition board (IDAQ)
Pamela Storage and Control Unit (PSCU)
3) Related topics:
software organization
housekeeping
Requirements & constraints
Trigger rate estimation:
- S1 x S2 x S3
12 Hz / G.F. = 20.5 cm2sr
Packet size per event:
6 KBytes (roughly), more then
40,000 analog channels
 6 downloads per day
 200 seconds connection
6
GByte
day
 speed
rate per
of 12 MBps
Data reduction solution
Trigger board
 Front end boards
Tracker
A/D
DSP
DSP
A/D
Calorimeter
A/D
DSP
DSP
A/D
Tof
A/D
 DSP boards
 Trigger board
 IDAQ board
 PSCU
PSCU
DSP
DSP
IDAQ
IDAQ
A/D
AC
A/D
DSP
DSP
A/D
A/D
ND
A/D
S4
Trigger-busy mechanism
S1
 Trigger board sends trigger to every
one, only if the idaq busy signal is
released.
S2
 Idaq starts in busy condition.
 Only at the end of settings
configurations will be sent a “release
busy” command
S3
busy
Power on
Idaq
Trigger
trigger
PSCU
Trigger
Triggerdelivered
vetoed
PSCU-IDAQ protocol
- Trigger mode
1) Settings before the acquisition:
- initialization
- Command queue selection
- calibration
2) DMA arming:
- Data timeout and Event timeout fixed
- Event header written in the Ram
3) Acquisition runs: cycled reloading of the command queue
Important: the cpu time consuming is
very low; the acquisition is managed
by the IDAQ (no interrupt handling)
Event acquisition overview
PSCU
1) Pamela starts up: the Idaq is busy
2) First command is sent: RELEASE BUSY
3) First trigger comes and Idaq goes again
in “busy” state.
Not busy
IDAQ
4) The read commands are hanging on
because idaq will release the acknoledge to
the PIF only after 3.5 ms from the trigger
5) All the “read event” commands are sent
to all subdetectors
6) Once the whole data are stored in PIF
Ram, the “DATA TIMEOUT” interrupt
will tell the cpu that the acquisition has
finished.
FE
FE
FE
Event acquisition overview
Vetoed triggers
Idaq trigger
Idaq busy
cmd strb
cmd ack
daq strb
daq ack
3.5 ms timeout: for compression algorithm
Answers from
DSP boards
Commands to
DSP boards
IDAQ : interface data acquisition
RS
422
LVDS
DSP controller e
checker PM & DM
ALARM
RS
422
TX Mux
1 in - 14 out
Async interfaces
MAIN controller e
multiplexer
Status & PWR
TTL
IN-Buffers
RX Mux
LVDS
TTL
14 in - 1 out
TTL
FLASH CTRL con
Hamming codec
FLASH
1Mx8
FLASH
1Mx8
RAM CTRL con
Hamming codec
SRAM
512Kx8
SRAM
512Kx8
CMD Buffer
TTL
DAQ Buffer
LVDS
OUT-Buffers
BUSY
RESET
ADSP2187
TRIGG
LVDS
LVDS
IDAQ : interface data acquisition
Ram controller
clk_tx
tx
end_tx
RAMSERCLK
rx
end_cmd
RAMRES
cmd_nda
MCLK
cmd_err
RAM_ERR
A[17..0]
D[7..0]
DEC_CMD
AR[17..0]
SERIAL
Interface
DR[7..0]
HAMMING
RAM
Interface
BHE
OEN
WEN
CEN
BLE
WERN
OERN
CERN
BHER
BLER
IDAQ : interface data acquisition
Flash controller
clk_tx
tx
end_tx
FLASHSERCLK
rx
end_cmd
FLASHRES
MCLK
cmd_err
Hamm_err
busy
AH [19..0]
DH [7..0]
DEC_CMD
AL [19..0]
SERIAL
Interface
DL [7..0]
HAMMING
FLASH
Interface
RYBYN_H
OEN_H
WEN_H
CEN_H
RESETN_H
RYBYN_L
OEN_L
WEN_L
CEN_L
RESETN_L
IDAQ : interface data acquisition
DSP controller
nIS
nIWR
nIAL
nIRD
clk_tx
tx
end_tx
DSPSERCLK
rx
end_cmd
cmd_nda
DSPRES
MCLK
checking
dsp_err
cmd_err
dat_err
busy
nIAD [15..0]
SERIAL
Interface
DEC_CMD
IDMA
Interface
nIACK
nRESET
nIRQL0
nPWD
FL0
FL1
FL2
CLKIN
mode [3..0]
PF4
PF6
PF7
PSCU
TC
TM
HKU
1553 MIL STD
CMD DAT TAM
CPU
PIF
PCMCIA BUS
Sys BUS
W BUS
R BUS
32
32
DC/DC
Mem
Mod
CPU module
1) Processor SPARC32 V7
2) SRAM 1M x 32 EDAC protected
3) Boot PROM
17 Mips @24 MHz
JTAG provided
CPU module
4) EEPROM 256K x 32
EDAC protected
5) MIL-STD 1553 Bus
Controller/Remote Terminal
Function with 64K x 16 Ram
buffer
6) CRIMEA: glue logic for
PCMCIA bus controller,
parallel S-90 bus interface
SSMM module
1) Eleven indipendent
memory columns
2) Each column is
composed by 4 Memory
Cubes
3) Each Cube is 8 x 8 MB
chip SDRAM
4) Eleven indipendent Current
Limiter for Latch-up protection
5) DRAMMA: Asic for DRAM
managing
8 modules for data
storage, 2 for ReedSolomon Check Symbols
and 1 for local
redundancy
PIF module
FPGA based interface (ALVARO):
1) CMD DMA management
2) DAQ DMA management
3) MM Parallel W/R bus
management
4) TAM DMA management
5) 1 programmable Event
Timeout
6) 1 programmable Data
Timeout
HKU module
House keeping unit: FPGA
based interface
commands
1) 2 serial links RS422
2) 24 High voltage commands (26 V)
3) 2 Differential Bi-level commands
acquisitions
1) 32 Contact closures
2) 8 Bi-level acquisition
3) 4 Differential Bi-level acquisition
4) 16 Analog double ended acquisition
5) 16 Analog double ended thermistors
6) 2 Serial Digital 16 bits acquisition
Considerations and conclusions
Considerations:
1) A lot more about housekeeping
2) Redundancy and SEU & SEL protection
3) Software organization
4) Power system
Conclusions:
1) Make it simple
2) Strong debug
3) HOPE IT WORKS!!!