ST7: Block Diagram
OSC1
OSC2
VDD
nRESET
INTERNAL
CLOCK
I2C
LVD
PORT A
POWER
SUPPLY
SPI
CONTROL
8 BIT CORE
ALU
PROGRAM
MEMORY
ADDRESS AND DATA BUS
VSS
MULTI OSC
+
CLOCK FILTER
PORT B
PA7..0
(8 bits)
PB7..0
(8 bits)
16-BIT TIMER A
PORT C
PC5..0
(6 bits)
8-BIT ADC
16-BIT TIMER B
RAM
WATCHDOG
Sistemi Elettronici Programmabili
13-1
ST72254 - Package
Sistemi Elettronici Programmabili
13-2
ST72254 Memory Map
Sistemi Elettronici Programmabili
13-3
ST72254 – Interrupt Vector
Sistemi Elettronici Programmabili
13-4
ST72254 Registers (1)
Sistemi Elettronici Programmabili
13-5
ST72254 Registers (2)
Sistemi Elettronici Programmabili
13-6
ST72254 Registers (IO)
Sistemi Elettronici Programmabili
13-7
ST72254 Registers (Timer)
Sistemi Elettronici Programmabili
13-8
ST72254 Registers (ADC)
Sistemi Elettronici Programmabili
13-9
IO Port: Block Diagram
Sistemi Elettronici Programmabili
13-10
IO Port Configurations - Input
Sistemi Elettronici Programmabili
13-11
IO Port Configurations – Output Opendrain
Sistemi Elettronici Programmabili
13-12
IO Port Configurations – Output Push Pull
Sistemi Elettronici Programmabili
13-13
IO Port: Registers
Sistemi Elettronici Programmabili
13-14
ADC: Overview (1)
•
8-BIT SUCCESSIVE APPROXIMATIONS CONVERTER WITH UP TO 8
ANALOG CHANNELS
•
FEATURE :
– Accuracy : 1 LSB
– Total Unajusted Error MAX : 1 LSB
– Conversion time : 24 CPU cycle ie 3µs at full speed (8MHz)
•
FLAGS
– COCO : end of conversion (Status flag)
– ADON : ADC on/off bit (to reduce power consumption)
Sistemi Elettronici Programmabili
13-15
ADC: Overview (2)
•
LOW CONSUMPTION MODES
– Wait mode doesn't affect the ADC
– Halt mode stops the ADC.
•
HARDWARE
– ST72334 and ST725xx : Vdda and Vssa must be connected
externally respectivelly to Vdd and Vss through decoupling
capacitors.
– ST72254 : connection done internally
•
RATIOMETRIC In the Functionnal Range
– If analog voltage input > Vdd :
converted result = FFh (no overflow indication)
– If analog voltage input < Vss :
converted result = 00h (no underflow indication)
Sistemi Elettronici Programmabili
13-16
ADC: Block Diagram
Sistemi Elettronici Programmabili
13-17
ADC: Registers
Sistemi Elettronici Programmabili
13-18
Timer: Block Diagram
Sistemi Elettronici Programmabili
13-19
Timer: Block Diagram (H)
Sistemi Elettronici Programmabili
13-20
Timer: Block Diagram (L)
Sistemi Elettronici Programmabili
13-21
Timer: Read Sequence
Sistemi Elettronici Programmabili
13-22
Timer: Input Capture
Sistemi Elettronici Programmabili
13-23
Timer: Output Compare
Sistemi Elettronici Programmabili
13-24
TIMER: PWM Mode
•
Automatic generation of a Pulse Width Modulated signal
•
Period &pulse lenght set by software:
– The first Output Compare Register OC1R contains the length of
the pulse
– The second Output Compare Register OCR2 contains the period
of the pulse
•
Resolution up to 100 steps at 20 KHz (fCPU =4 MHz): 1% of accuracy
on the duty cycle
t
T
Sistemi Elettronici Programmabili
13-25
Timer: PWM Flow
 Free running counter is
When the free running counter
reaches
OC2R register value
initialized to FFFCh
 OLVL2 bit level is applied on
the OCMP1 pin
 ICF1 bit is set
When the free running counter
reaches
OC1R register value
Sistemi Elettronici Programmabili
 OLVL1 bit level is applied on
the OCMP1 pin
13-26
Timer: PWM Counter
FREE RUNNING
COUNTER VALUE
Tmax = Ttimer × 65535
FFFFh
FFFCh
Compare 2
Compare 1
0000h
time
OLVL2= 1
OCMP1
Ouput Compare pin
Timer output
OLVL1=0
Sistemi Elettronici Programmabili
time
13-27
Timer: CR1
Sistemi Elettronici Programmabili
13-28
Timer: CR2
Sistemi Elettronici Programmabili
13-29
Timer: SR
Sistemi Elettronici Programmabili
13-30
Schmitt Trigger: Caratteristica Inverter
Vin
t
Vout
Sistemi Elettronici Programmabili
t
13-31
Schmitt Trigger: Caratteristica
Vout
Vin
Sistemi Elettronici Programmabili
13-32
Schmitt Trigger: Inverter - Commutazioni Spurie
Vin
t
Vout
Sistemi Elettronici Programmabili
t
13-33
Schmitt Trigger: Commutazione
Vin
t
Vout
Sistemi Elettronici Programmabili
t
13-34