Microelettronica
Anno Accademico 2006-2007
Prof. Adelio Salsano
Presentazione e programma del
corso
1: Introduction
CMOS VLSI Design
Slide 1
OBIETTIVO
Tecnologie, blocchi elementari e architetture per
l’analisi e la sintesi di circuiti e sistemi microelettronici
ALTERNATIVE
Circuiti non programmabili
Circuiti programmabili
Circuiti dedicati
Soluzioni miste
Il corso fornisce le competenze necessarie per la valutazione
delle prestazioni di circuiti e sistemi elettronici come
prerequisito per la sintesi
1: Introduction
CMOS VLSI Design
Slide 2
Notizie sul corso
Orario
Mercoledì
Giovedì
Venerdì
11,30
11,30
11,30
Aula 9
Aula 7
Aula 12
Materiale didattico
 Diapositive lezioni
 N.H.E. Weste, D. Harris “Principles of CMOS VLSI Design”,
Addison Wesley
 R. L. Geiger, P.E. Allen, N.R. Strader VLSIdesign techniques
for analog and digital Circuits, Mac Graw Hill Int. Ed.
1: Introduction
CMOS VLSI Design
Slide 3
PROGRAMMA DEL CORSO




Introduzione
Considerazioni generali
Aspetti tecnici ed economici
Richiami circuitali:
– Inverter, NAND, NOR
– Pass transistor, transmission gate
– Latch, flip flop
– Regole di progetto
 Il transistor MOS
– Caratteristiche I-V
– Caratteristiche C-V
– Modelli delle capacità G,S,D
– Effetti non ideali
1: Introduction
CMOS VLSI Design
Slide 4
(segue Programma)
 Inverter CMOS
– Caratteristiche in DC
– Beta, rapporto dei beta, margini di rumore
– Inverter dipendenti dal rapporto dei beta
 Inverter a pass transistor e tristate
 Modelli RC di ritardo
 Tecnologie CMOS:
– Litografia,formazione del canale, ossidazione, contatti e
metallizzazione
– Regole di progetto
 Elementi circuitali: transistor, caoacità, resistenze,
transistor bipolari, memorie
1: Introduction
CMOS VLSI Design
Slide 5
(segue Programma)
 Stima delle prestazioni
– Ritardi dei circuiti elementari: sforzo logico
– Dissipazione di potenza
– nterconnessioni
– Margini progettuali
 Affidabilità e diagnostica dei circuiti integrati:
– elettromigrazione, riscaldamento, latchup
– guasti transitori e permanenti
– testing on line e off line
– modelli di guasto
– design for testability
1: Introduction
CMOS VLSI Design
Slide 6
(segue Programma)






La simulazione circuitale: SPICE
Logica a pass transistor
Circuiti BICMOS
Confronto tra le famiglie
Logica statica e dinamica
Sistemi digitali complessi: latch, flip flop, sincronizzazione
– microprocessori, memorie, logica programmabile
 Circuiti e sistemi analogici:
– Interruttori e resistenze attive
– specchio di corrente
– riferimenti di corrente e tensione
– amplificatori invertenti e differenziali
– amplificatore operazionale
1: Introduction
CMOS VLSI Design
Slide 7
Brief History
Till 1970 I.C. bipolar, afterwards MOSFET
SSI
1-100 MOS
MSI
100-1000 MOS
LSI
1000-100.000 MOS
VLSI
100.000 -106 MOS
ULSI
> 106 MOS
1: Introduction
CMOS VLSI Design
Slide 8
Brief History (cont.)
 1958: First integrated circuit
– Flip-flop using two transistors
– Built by Jack Kilby at Texas Instruments
 2003
– Intel Pentium 4 mprocessor (55 million transistors)
– 512 Mbit DRAM (> 0.5 billion transistors)
 53% compound annual growth rate over 45 years
– No other technology has grown so fast so long
 Driven by miniaturization of transistors
– Smaller is cheaper, faster, lower in power!
– Revolutionary effects on society
1: Introduction
CMOS VLSI Design
Slide 9
Vantaggi della tecnologia
integrata





Dimensioni: Fette di silicio (2003) fino a 12 pollici
Velocità
Consumo di potenza
Dimensioni del sistema
Costo del sistema
CHIP
Legge di MOORE: raddoppio ogni anno e mezzo del
numero di componenti per chip
1: Introduction
CMOS VLSI Design
Slide 10
MERCATO DEI CIRCUITI
INTEGRATI
1: Introduction
CMOS VLSI Design
Slide 11
COMPLESSITA’ MICRO INTEL
1: Introduction
CMOS VLSI Design
Slide 12
FREQUENZE
1: Introduction
MICRO INTEL
CMOS VLSI Design
Slide 13
Silicon Lattice
 Transistors are built on a silicon substrate
 Silicon is a Group IV material
 Forms crystal lattice with bonds to four neighbors
1: Introduction
Si
Si
Si
Si
Si
Si
Si
Si
Si
CMOS VLSI Design
Slide 14
Dopants





Silicon is a semiconductor
Pure silicon has no free carriers and conducts poorly
Adding dopants increases the conductivity
Group V: extra electron (n-type)
Group III: missing electron, called hole (p-type)
1: Introduction
Si
Si
Si
Si
Si
Si
As
Si
Si
B
Si
Si
Si
Si
Si
-
+
+
-
CMOS VLSI Design
Si
Si
Si
Slide 15
p-n Junctions
 A junction between p-type and n-type semiconductor
forms a diode.
 Current flows only in one direction
1: Introduction
p-type
n-type
anode
cathode
CMOS VLSI Design
Slide 16
nMOS Transistor
 Four terminals: gate, source, drain, body
 Gate – oxide – body stack looks like a capacitor
– Gate and body are conductors
– SiO2 (oxide) is a very good insulator
– Called metal – oxide – semiconductor (MOS)
capacitor
Source
Gate
Drain
Polysilicon
– Even though gate is
SiO2
no longer made of metal
n+
n+
p
1: Introduction
CMOS VLSI Design
bulk Si
Slide 17
nMOS Operation
 Body is commonly tied to ground (0 V)
 When the gate is at a low voltage:
– P-type body is at low voltage
– Source-body and drain-body diodes are OFF
– No current flows, transistor is OFF
Source
Gate
Drain
Polysilicon
SiO2
0
n+
n+
S
p
1: Introduction
D
bulk Si
CMOS VLSI Design
Slide 18
nMOS Operation Cont.
 When the gate is at a high voltage:
– Positive charge on gate of MOS capacitor
– Negative charge attracted to body
– Inverts a channel under gate to n-type
– Now current can flow through n-type silicon from
source through channel to drain, transistor is ON
Source
Gate
Drain
Polysilicon
SiO2
1
n+
n+
S
p
1: Introduction
D
bulk Si
CMOS VLSI Design
Slide 19
pMOS Transistor
 Similar, but doping and voltages reversed
– Body tied to high voltage (VDD)
– Gate low: transistor ON
– Gate high: transistor OFF
– Bubble indicates inverted behavior
Source
Gate
Drain
Polysilicon
SiO2
p+
p+
n
1: Introduction
CMOS VLSI Design
bulk Si
Slide 20
Power Supply Voltage
 GND = 0 V
 In 1980’s, VDD = 5V
 VDD has decreased in modern processes
– High VDD would damage modern tiny transistors
– Lower VDD saves power
 VDD = 3.3, 2.5, 1.8, 1.5, 1.2, 1.0, …
1: Introduction
CMOS VLSI Design
Slide 21
Transistors as Switches
 We can view MOS transistors as electrically
controlled switches
 Voltage at gate controls path from source to drain
d
nMOS
pMOS
g=1
d
d
OFF
g
ON
s
s
s
d
d
d
g
OFF
ON
s
1: Introduction
g=0
s
CMOS VLSI Design
s
Slide 22
CMOS Inverter
A
VDD
Y
0
1
A
A
Y
Y
GND
1: Introduction
CMOS VLSI Design
Slide 23
CMOS Inverter
A
VDD
Y
0
1
OFF
0
A=1
Y=0
ON
A
Y
GND
1: Introduction
CMOS VLSI Design
Slide 24
CMOS Inverter
A
Y
0
1
1
0
VDD
ON
A=0
Y=1
OFF
A
Y
GND
1: Introduction
CMOS VLSI Design
Slide 25
CMOS NAND Gate
A
B
0
0
0
1
1
0
1
1
Y
Y
A
B
1: Introduction
CMOS VLSI Design
Slide 26
CMOS NAND Gate
A
B
Y
0
0
1
0
1
1
0
1
1
1: Introduction
ON
ON
Y=1
A=0
B=0
CMOS VLSI Design
OFF
OFF
Slide 27
CMOS NAND Gate
A
B
Y
0
0
1
0
1
1
1
0
1
1
1: Introduction
OFF
ON
Y=1
A=0
B=1
CMOS VLSI Design
OFF
ON
Slide 28
CMOS NAND Gate
A
B
Y
0
0
1
0
1
1
1
0
1
1
1
1: Introduction
ON
A=1
B=0
CMOS VLSI Design
OFF
Y=1
ON
OFF
Slide 29
CMOS NAND Gate
A
B
Y
0
0
1
0
1
1
1
0
1
1
1
0
1: Introduction
OFF
A=1
B=1
CMOS VLSI Design
OFF
Y=0
ON
ON
Slide 30
CMOS NOR Gate
A
B
Y
0
0
1
0
1
0
1
0
0
1
1
0
1: Introduction
A
B
Y
CMOS VLSI Design
Slide 31
3-input NAND Gate
 Y pulls low if ALL inputs are 1
 Y pulls high if ANY input is 0
1: Introduction
CMOS VLSI Design
Slide 32
3-input NAND Gate
 Y pulls low if ALL inputs are 1
 Y pulls high if ANY input is 0
Y
A
B
C
1: Introduction
CMOS VLSI Design
Slide 33
CMOS Fabrication
 CMOS transistors are fabricated on silicon wafer
 Lithography process similar to printing press
 On each step, different materials are deposited or
etched
 Easiest to understand by viewing both top and
cross-section of wafer in a simplified manufacturing
process
1: Introduction
CMOS VLSI Design
Slide 34
Inverter Cross-section
 Typically use p-type substrate for nMOS transistors
 Requires n-well for body of pMOS transistors
A
GND
VDD
Y
SiO2
n+ diffusion
n+
n+
p+
p+
n well
p substrate
nMOS transistor
1: Introduction
p+ diffusion
polysilicon
metal1
pMOS transistor
CMOS VLSI Design
Slide 35
Well and Substrate Taps
 Substrate must be tied to GND and n-well to VDD
 Metal to lightly-doped semiconductor forms poor
connection called Schottky Diode
 Use heavily doped well and substrate contacts / taps
A
GND
VDD
Y
p+
n+
n+
p+
p+
n+
n well
p substrate
substrate tap
1: Introduction
well tap
CMOS VLSI Design
Slide 36
Inverter Mask Set
 Transistors and wires are defined by masks
 Cross-section taken along dashed line
A
Y
GND
VDD
nMOS transistor
pMOS transistor
well tap
substrate tap
1: Introduction
CMOS VLSI Design
Slide 37
Detailed Mask Views
 Six masks
– n-well
– Polysilicon
– n+ diffusion
– p+ diffusion
– Contact
– Metal
n well
Polysilicon
n+ Diffusion
p+ Diffusion
Contact
Metal
1: Introduction
CMOS VLSI Design
Slide 38
Fabrication Steps
 Start with blank wafer
 Build inverter from the bottom up
 First step will be to form the n-well
– Cover wafer with protective layer of SiO2 (oxide)
– Remove layer where n-well should be built
– Implant or diffuse n dopants into exposed wafer
– Strip off SiO2
p substrate
1: Introduction
CMOS VLSI Design
Slide 39
Oxidation
 Grow SiO2 on top of Si wafer
– 900 – 1200 C with H2O or O2 in oxidation furnace
SiO2
p substrate
1: Introduction
CMOS VLSI Design
Slide 40
Photoresist
 Spin on photoresist
– Photoresist is a light-sensitive organic polymer
– Softens where exposed to light
Photoresist
SiO2
p substrate
1: Introduction
CMOS VLSI Design
Slide 41
Lithography
 Expose photoresist through n-well mask
 Strip off exposed photoresist
Photoresist
SiO2
p substrate
1: Introduction
CMOS VLSI Design
Slide 42
Etch
 Etch oxide with hydrofluoric acid (HF)
– Seeps through skin and eats bone; nasty stuff!!!
 Only attacks oxide where resist has been exposed
Photoresist
SiO2
p substrate
1: Introduction
CMOS VLSI Design
Slide 43
Strip Photoresist
 Strip off remaining photoresist
– Use mixture of acids called piranah etch
 Necessary so resist doesn’t melt in next step
SiO2
p substrate
1: Introduction
CMOS VLSI Design
Slide 44
n-well
 n-well is formed with diffusion or ion implantation
 Diffusion
– Place wafer in furnace with arsenic gas
– Heat until As atoms diffuse into exposed Si
 Ion Implanatation
– Blast wafer with beam of As ions
– Ions blocked by SiO2, only enter exposed Si
SiO2
n well
1: Introduction
CMOS VLSI Design
Slide 45
Strip Oxide
 Strip off the remaining oxide using HF
 Back to bare wafer with n-well
 Subsequent steps involve similar series of steps
n well
p substrate
1: Introduction
CMOS VLSI Design
Slide 46
Polysilicon
 Deposit very thin layer of gate oxide
– < 20 Å (6-7 atomic layers)
 Chemical Vapor Deposition (CVD) of silicon layer
– Place wafer in furnace with Silane gas (SiH4)
– Forms many small crystals called polysilicon
– Heavily doped to be good conductor
Polysilicon
Thin gate oxide
n well
p substrate
1: Introduction
CMOS VLSI Design
Slide 47
Polysilicon Patterning
 Use same lithography process to pattern polysilicon
Polysilicon
Polysilicon
Thin gate oxide
n well
p substrate
1: Introduction
CMOS VLSI Design
Slide 48
Self-Aligned Process
 Use oxide and masking to expose where n+ dopants
should be diffused or implanted
 N-diffusion forms nMOS source, drain, and n-well
contact
n well
p substrate
1: Introduction
CMOS VLSI Design
Slide 49
N-diffusion
 Pattern oxide and form n+ regions
 Self-aligned process where gate blocks diffusion
 Polysilicon is better than metal for self-aligned gates
because it doesn’t melt during later processing
n+ Diffusion
n well
p substrate
1: Introduction
CMOS VLSI Design
Slide 50
N-diffusion cont.
 Historically dopants were diffused
 Usually ion implantation today
 But regions are still called diffusion
n+
n+
n+
n well
p substrate
1: Introduction
CMOS VLSI Design
Slide 51
N-diffusion cont.
 Strip off oxide to complete patterning step
n+
n+
n+
n well
p substrate
1: Introduction
CMOS VLSI Design
Slide 52
P-Diffusion
 Similar set of steps form p+ diffusion regions for
pMOS source and drain and substrate contact
p+ Diffusion
p+
n+
n+
p+
p+
n+
n well
p substrate
1: Introduction
CMOS VLSI Design
Slide 53
Contacts
 Now we need to wire together the devices
 Cover chip with thick field oxide
 Etch oxide where contact cuts are needed
Contact
Thick field oxide
p+
n+
n+
p+
p+
n+
n well
p substrate
1: Introduction
CMOS VLSI Design
Slide 54
Metalization
 Sputter on aluminum over whole wafer
 Pattern to remove excess metal, leaving wires
Metal
Metal
Thick field oxide
p+
n+
n+
p+
p+
n+
n well
p substrate
1: Introduction
CMOS VLSI Design
Slide 55
Layout
 Chips are specified with set of masks
 Minimum dimensions of masks determine transistor
size (and hence speed, cost, and power)
 Feature size f = distance between source and drain
– Set by minimum width of polysilicon
 Feature size improves 30% every 3 years or so
 Normalize for feature size when describing design
rules
 Express rules in terms of l = f/2
– E.g. l = 0.3 mm in 0.6 mm process
1: Introduction
CMOS VLSI Design
Slide 56
Simplified Design Rules
 Conservative rules to get you started
1: Introduction
CMOS VLSI Design
Slide 57
Inverter Layout
 Transistor dimensions specified as Width / Length
– Minimum size is 4l / 2l, sometimes called 1 unit
– In f = 0.6 mm process, this is 1.2 mm wide, 0.6 mm
long
1: Introduction
CMOS VLSI Design
Slide 58
Summary




MOS Transistors are stack of gate, oxide, silicon
Can be viewed as electrically controlled switches
Build logic gates out of switches
Draw masks to specify layout of transistors
 Now you know everything necessary to start
designing schematics and layout for a simple chip!
1: Introduction
CMOS VLSI Design
Slide 59