CMOS
Manufacturing
Process
Elettronica D. AA 2000-2001
Manufacturing Process
Digital Integrated Circuits© Prentice Hall 1995
CMOS Process
Elettronica D. AA 2000-2001
Manufacturing Process
Digital Integrated Circuits© Prentice Hall 1995
CMOS Inverter Layout
In
GND
VD D
A
A’
Out
(a) Layout
A
A’
n
p-substrate
+
n
+
p
Field
Oxide
(b) Cross-Section along A-A’
Elettronica D. AA 2000-2001
Manufacturing Process
Digital Integrated Circuits© Prentice Hall 1995
Patterning on Si
Elettronica D. AA 2000-2001
Manufacturing Process
Digital Integrated Circuits© Prentice Hall 1995
Semiconductor fabrication (1)
2
Elettronica D. AA 2000-2001
Manufacturing Process
Digital Integrated Circuits© Prentice Hall 1995
Semiconductor Fabrication (2)
1
3
4
Elettronica D. AA 2000-2001
Manufacturing Process
Digital Integrated Circuits© Prentice Hall 1995
Semiconductor Fabrication (3)
3
3
Elettronica D. AA 2000-2001
Manufacturing Process
Digital Integrated Circuits© Prentice Hall 1995
Semiconductor Fabrication (4)
4
END
Elettronica D. AA 2000-2001
Manufacturing Process
Digital Integrated Circuits© Prentice Hall 1995
Circuit Under Design
VDD
VDD
M2
M4
Vout
Vin
M1
Vout2
M3
This two-inverter circuit (of Figure 3.25 in the text) will be
manufactured in a twin-well process.
Elettronica D. AA 2000-2001
Manufacturing Process
Digital Integrated Circuits© Prentice Hall 1995
Circuit Layout
B4
B2
pMOS-1
Vdd
S2
Inverter 1
nMOS-1
pMOS-1
G2
S4
G4
IN2=OUT1
D4
D2
Inverter 2
nMOS-2
pMOS-2
pMOS-2
IN1
Inverter 1
OUT1
D1
G1
S1
nMOS-1
Elettronica D. AA 2000-2001
B1
Manufacturing Process
IN2
OUT2
Inverter 2
D3
G3
S3
B3
GND
nMOS-2
Digital Integrated Circuits© Prentice Hall 1995
Start Material
A
pMOS
Starting wafer: n-type with
nMOS
A
13
A’
doping level = 10
/cm
* Cross-sections will be
shown along vertical line
Si n-type
Elettronica D. AA 2000-2001
A’
3
Manufacturing Process
A-A’
Digital Integrated Circuits© Prentice Hall 1995
N-well Construction
pMOS
(1) Oxidize wafer
(2) Deposit silicon nitride
(3) Deposit photoresist
nMOS
photoresist
Si n-type
Elettronica D. AA 2000-2001
Manufacturing Process
silicon nitride
silicon dioxide
Digital Integrated Circuits© Prentice Hall 1995
N-well Construction
pMOS
(4) Expose resist
using
n-well mask
nMOS
Exposed resist
Si n type
Elettronica D. AA 2000-2001
Manufacturing Process
Digital Integrated Circuits© Prentice Hall 1995
N-well Construction
pMOS
nMOS
(5) Develop resist
(6) Etch nitride and
(7) Grow thick oxide
Si n type
Elettronica D. AA 2000-2001
Manufacturing Process
Digital Integrated Circuits© Prentice Hall 1995
N-well Construction
pMOS
(8) Implant n-dopants
nMOS
(phosphorus)
(up to 1.5 mm deep)
thick oxide
n-well
Si n type
Elettronica D. AA 2000-2001
Manufacturing Process
Digital Integrated Circuits© Prentice Hall 1995
P-well Construction
pMOS
Repeat previous steps
nMOS
pMOS
nMOS
n-well
p-well
Si n type
Elettronica D. AA 2000-2001
Manufacturing Process
Digital Integrated Circuits© Prentice Hall 1995
Grow Gate Oxide
pMOS
nMOS
Gate oxide
55 nm thin
pMOS
nMOS
n-well
p-well
Si n type
Elettronica D. AA 2000-2001
Manufacturing Process
Digital Integrated Circuits© Prentice Hall 1995
Grow Thick Field Oxide
pMOS
Field Oxide
0.9 mm thick
nMOS
Uses Active Area mask
pMOS
nMOS
n-well
p-well
Is followed by
threshold-adjusting
implants
Si n type
Elettronica D. AA 2000-2001
Manufacturing Process
Digital Integrated Circuits© Prentice Hall 1995
Polysilicon layer
pMOS
Polysilicon Deposition
nMOS
pMOS
nMOS
n-well
p-well
Si n type
Elettronica D. AA 2000-2001
Manufacturing Process
Digital Integrated Circuits© Prentice Hall 1995
Source-Drain Implants
n+ source-drain implant
(using n+ select mask)
pMOS
photoresist
nMOS
pMOS
nMOS
n-well
p-well
Si n type
Elettronica D. AA 2000-2001
Manufacturing Process
n+ source-drain implant
(using n+ select mask)
Digital Integrated Circuits© Prentice Hall 1995
Source-Drain Implants
pMOS
p+ source-drain implant
(using p+ select mask)
nMOS
pMOS
B
S
G
nMOS
D
D
n-well
G
S
B
p-well
Si n type
Elettronica D. AA 2000-2001
Manufacturing Process
Digital Integrated Circuits© Prentice Hall 1995
Contact-Hole Definition
(1) Deposit inter-level
Dielectric
(SiO2) — 0.75 mm
(2) Define contact
opening
using contact mask
pMOS
nMOS
pMOS
nMOS
n-well
p-well
Si n type
Elettronica D. AA 2000-2001
Manufacturing Process
Digital Integrated Circuits© Prentice Hall 1995
Aluminum-1 Layer
pMOS
Aluminum evaporated
(0.8 mm thick)
OUT
IN
followed by other metal
layers and glass
nMOS
Vdd
B
GND
IN
S
G
D
G
pMOS
Elettronica D. AA 2000-2001
OUT
D
G
S
B
nMOS
Manufacturing Process
Digital Integrated Circuits© Prentice Hall 1995
Advanced Metalization
Elettronica D. AA 2000-2001
Manufacturing Process
Digital Integrated Circuits© Prentice Hall 1995
Intel 0.09 mm Generation
Elettronica D. AA 2000-2001
Manufacturing Process
Digital Integrated Circuits© Prentice Hall 1995
Downsizing MOSFET below 0.1 mm
Elettronica D. AA 2000-2001
Manufacturing Process
Digital Integrated Circuits© Prentice Hall 1995
Design Rules
Elettronica D. AA 2000-2001
Manufacturing Process
Digital Integrated Circuits© Prentice Hall 1995
Design Rules



Interface between designer and process
engineer
Guidelines for constructing process masks
Unit dimension: Minimum line width
» scalable design rules: lambda parameter
» absolute dimensions (micron rules)
Elettronica D. AA 2000-2001
Manufacturing Process
Digital Integrated Circuits© Prentice Hall 1995
CMOS Process Layers
Layer
Color
Well (p,n)
Yellow
Active Area (n+,p+)
Green
Select (p+,n+)
Green
Polysilicon
Red
Metal1
Blue
Metal2
Magenta
Contact To Poly
Black
Contact To Diffusion
Black
Via
Black
Elettronica D. AA 2000-2001
Manufacturing Process
Representation
Digital Integrated Circuits© Prentice Hall 1995
Intra-Layer Design Rules
Same Potential
0
or
6
Well
Different Potential
2
9
Polysilicon
2
10
3
Active
Contact
or Via
Hole
3
2
3
Metal1
2
3
2
Select
4
Metal2
3
Elettronica D. AA 2000-2001
Manufacturing Process
Digital Integrated Circuits© Prentice Hall 1995
Transistor
Transistor Layout
Transistor
1
3
2
5
Elettronica D. AA 2000-2001
Manufacturing Process
Digital Integrated Circuits© Prentice Hall 1995
Via’s and Contacts
2
4
Via
1
1
5
Metal to
1
Active Contact
Metal to
Poly Contact
3
2
2
2
Elettronica D. AA 2000-2001
Manufacturing Process
Digital Integrated Circuits© Prentice Hall 1995
Select Layer
2
3
Select
2
1
3
3
2
5
Well
Substrate
Elettronica D. AA 2000-2001
Manufacturing Process
Digital Integrated Circuits© Prentice Hall 1995