Chapter 12
Analog Integrated Circuits
Microelectronic Circuit Design
Richard C. Jaeger
Travis N. Blalock
Chap 12 - 1
2 Microelettronica – Circuiti integrati analogici 2/ed
Richard C. Jaeger, Travis N. Blalock
Copyright © 2005 – The McGraw-Hill Companies srl
Chapter Goals
• Understand bipolar and MOS current mirror operation and mirror ratio errors.
• Explore high output resistance current sources including cascode and Wilson
current sources.
• Design current sources for both discrete and integrated applications.
• Study reference current circuits such as VBE-based reference, bandgap
reference and Widlar current source.
• Use current mirrors as active loads in differential amplifiers to increase
voltage gain of single-stage amplifiers.
• Study effects of device mismatch on amplifier performance.
• Analyze design of classic mA741 op amp.
• Study realization of four-quadrant analog multipliers with large input signal
range.
• Increase understanding of SPICE simulation techniques.
2 Microelettronica – Circuiti integrati analogici 2/ed
Richard C. Jaeger, Travis N. Blalock
Copyright © 2005 – The McGraw-Hill Companies srl
MOS Current Mirrors: DC Analysis
2I
REF
V
V 
TN
GS1
K (1 lV
)
n1
DS1
K 
2


I  I  n V
V  1 lV

TN  
O D2
 GS2
DS2

2
1 lV
DS2  I
I  I
REF
O REF
1 lV
DS1


MOSFETs M1 and M2 are
assumed to have identical VTN,
Kn’, l, and W/L ratios.
IREF provides operating bias to
mirror.
VDS1 = VGS1= VGS2 =VGS
2 Microelettronica – Circuiti integrati analogici 2/ed
Richard C. Jaeger, Travis N. Blalock


However, due to mismatches, VDS1 is
not equal to VDS2 and there is slight
mismatch between output and
reference currents. Mirror ratio is:


1 lV
DS2
O
MR 

I
REF 1 lVDS1
I


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MOS Current Mirror (Example)
Problem:Calculate output current for given current mirror.
Given data: IREF = 150 mA, VSS = 10 V, VTN = 1 V, Kn = 250
mA/V2, l = 0.0133 V-1
Analysis: (1+ l VDS1) term is neglected to simplify dc bias
calculation.
V
V
V

DS1 GS1 TN
2I
REF  1V  2(150μA)  2.10V
Kn
μA
250
V2


1  0.0133 (10V) 


V


I  (150μA)
 165μA
O


0
.
0133
1 
(2.10V) 

V


Actual currents are found to be mismatched by approximately 10%.
2 Microelettronica – Circuiti integrati analogici 2/ed
Richard C. Jaeger, Travis N. Blalock
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MOS Current Mirrors: Changing Mirror
Ratio
W


K  Kn'  
n1
 L 1




K  Kn' W 
n2
 L 2
1 lV
n2
DS2
I  I
O REF
K 1 lV
n1
DS1
W 

 1  lV


DS2
 L 2
I
REF  W 
1 lV


DS1
 L 1
K
Mirror ratio can be changed by
modifying W/L ratios of the two
transistors forming the mirror.




W
1 lV


DS2
L
2
MR 
W
1 lV


DS1
L 1


















In given current mirror, Io =5IREF. Again
mismatch in VDS causes error in MR.
2 Microelettronica – Circuiti integrati analogici 2/ed
Richard C. Jaeger, Travis N. Blalock
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Bipolar Current Mirrors: DC Analysis




V

V

V


V

CE
2
BE

I  I exp BE 1 CE1  IC 2  I S exp V 1


C1 S
V
V

V
T 


T

A

A 






V


V


CE
2


b
b
CE
1
1

b b
1


F2
FO 

V
F1
FO 



V


A


A


V

I
V

I
S exp BE 


I

S
BE
I 
exp

B1 b
 V

B1 b
 V

T 

T


FO
FO
1  (V
/V )
BJTs Q1 and Q2 are assumed to
CE2 A
I  I
REF
O
have identical IS, VA, bFO, and
1 VCE2  2 
 V

W/L ratios.
b

A
FO 













Io = IC2,
IB2
IREF = IC1 + IB1 +
VBE1= VBE2 =VBE
2 Microelettronica – Circuiti integrati analogici 2/ed
Richard C. Jaeger, Travis N. Blalock

Finite current gain of BJT causes slight
mismatch between Io and IREF.
MR 
IO
1

I REF 1(2 / b FO )
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Current Mirror (Example)
Problem:Calculate and compare mirror ratios for BJT and
MOS current mirror.
Given data: IREF = 150 mA, VGS = 2 V, VDS2 = VCE2 = 10 V, l
= 0.02 V-1 VA = 50 V, bFO = 100, VSS = 10 V, M1 = M2, Q1 =
1  lV
Q2.
DS2  1.15
MR

MOS
1  lV
Analysis:
MR
BJT

2 Microelettronica – Circuiti integrati analogici 2/ed
Richard C. Jaeger, Travis N. Blalock


 DS1 
1 (VCE2 /VA)
1 VCE2  2 
 V

b

A
FO 
 1.16
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Bipolar Current Mirrors: Changing Mirror
Ratio
Emitter area scaling changes the
transport equations using which,
I  nI
REF
O
1 (VCE2 /VA)
1 VCE2  1 n 
 V

b

A
FO 
A
n  E2
A
E1
Ideally, MR= n, but for finite gain,
MR 
Mirror ratio can be changed by
modifying the emitter area of the
transistor.
A
E
I I
S SO
A
2 Microelettronica – Circuiti integrati analogici 2/ed
Richard C. Jaeger, Travis N. Blalock
n
1
n
b
FO
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Multiple Current Sources
• Reference current enters diodeconnected transistor M1 establishing
gate-source voltage to bias M2 through
M5, each with different W/L ratio.
• Absence of current gain defect permits
large number of MOSFETs to be
driven by one reference transistor.
• Similar multiple bipolar sources can
be built from one reference BJT.
• As base current error term worsens
when more BJTs are added, umber of
outputs of basic bipolar mirror are
limited.
2 Microelettronica – Circuiti integrati analogici 2/ed
Richard C. Jaeger, Travis N. Blalock
Copyright © 2005 – The McGraw-Hill Companies srl
Buffered Bipolar Current Mirror
Assuming infinite Early voltage for simplicity,
I
(1 n) C1
b
FO1
I I
I I

C1 REF B3 REF
1 b
FO3

When large mirror ratio is used or
if many source currents are
generated from one reference BJT,
current gain defect worsens.
Current gain of Q3 is used to
reduce base current that is
subtracted from reference current.
2 Microelettronica – Circuiti integrati analogici 2/ed
Richard C. Jaeger, Travis N. Blalock
I  nI  nI
REF
O
C1

1
(1 n)
1
b
(1 b
)
FO1
FO3
Thus error term in denominator is
reduced.
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Output Resistance of Current Mirrors
This simplifies the ac model of
the current mirror. Similar
analysis applies to MOSFET
current mirror except that the
current gain is infinite. Thus
Rout  r
o2
1
V V
V

or
CS A2
CS l
2
For diode connected BJT, from
small-signal model,
i  ( gm  go  g )v
v 1
R  
...If boand mF >>1
i gm
2 Microelettronica – Circuiti integrati analogici 2/ed
Richard C. Jaeger, Travis N. Blalock
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Two-port Model for Current Mirror
v
v
1
1
1
h  v1
0
h 


12
11 i
2 i 0
1 v 0 gm1  g 2 gm1
1
2
g r
g
i
i
1
2
m
2

2
m
2
2
h


h 


n
22 v2
21 i
1

g
r
g
1
i 0 ro2
v 0
m
1

2
m
1
Since current mirror has a
2
1
current input and current
output, we use h-parameters.
v h i h v
1 11 1 12 2
i h i h v
2 21 1 22 2
2 Microelettronica – Circuiti integrati analogici 2/ed
Richard C. Jaeger, Travis N. Blalock
For MOS current mirrors,
1
h 0
h 
12
11 g
m1
g
1
m
2
h

h 
n
22 r
21 g
o2
m1
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Bipolar Widlar Current Source
Current through R is given by:


I

I
V
V
V
 REF

S
2
BE
1
BE
2
T
I


ln

E2
R
R  I
I 
O
S1 

If transistors are matched,

I
A 
V
I  I
 T ln REF E 2 
F E2 R  I
O
A 

O
E1 

Rout  r 1 g R 
o2 
m2 
R in Widlar source allows
adjustment of mirror ratio.




























I
I
V ln 1 REF V ln REF
T
BE1 T
I
I
S1
S1


 I

I 

 O 
O
V
V ln 1
  V ln

T I
BE2 T


I


S 2 
S
2


V
2 Microelettronica – Circuiti integrati analogici 2/ed
Richard C. Jaeger, Travis N. Blalock














I
 r 1 ln REF
o2
 I
 O
V  KV
CS
A2
 
S 2    Kr
o2
I  
S1  
I
Typically 1 < K < 10.
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PTAT Voltage
• Voltage developed across R in Widlar current source is
directly proportional to absolute temperature.








 I
A 
A 
 C1
E 2 
V
V
V
V ln C1 E 2   kT
ln

PTAT
BE1 BE2 T
I
A  q  I
A 
C 2 E1 
C
2
E1 


 I
V
A  V
PTAT   k ln C1 E 2    PTAT
q I
T
A 
T

E1 
 C2
I
• Example: T = 300 K, IC1 = IC2 and AE2 = 10 AE1. Then
=59.6 mV with temperature coefficient of slightly< +0.2
mV/K
• PTAT voltage combined with A-D converter is the core of
electronic thermometers.
2 Microelettronica – Circuiti integrati analogici 2/ed
Richard C. Jaeger, Travis N. Blalock
Copyright © 2005 – The McGraw-Hill Companies srl
MOS Widlar Current Source




I
(
W
/
L
)
1
2
O 
1
O
1

I
(W / L) 
I
R I REF Kn1 
REF
2

REF
I
Current through R is given by:
If IO is known, IREF can be directly
calculated. If IREF , R and W/L ratios are
known, we can write a quadratic
equation in terms of IO / I REF
2I
O Small-signal model for MOS Widlar
REF 
source represents a C-S stage with
K
K
V
V
n
1
n
2
GS
1
GS
2
I 

resistor R in its source.
O
R
R



I
(W / L) 
1 g

1 2 I REF 

R

r
R

O
1


1

out
o2
m2 


K
I
(
W
/
L
)
R
REF
n1 
2 
2I
2 Microelettronica – Circuiti integrati analogici 2/ed
Richard C. Jaeger, Travis N. Blalock
Copyright © 2005 – The McGraw-Hill Companies srl
MOS Wilson Current Source
where
V
V

TN
GS
2I
REF
K
n1
From small-signal model,
vx  v  v
3 1
  i x  g
During operation, all
transistors are in active
region. ID2 = IREF , ID3 = ID1
= IO, VGS3 = VGS1=VGS
1  2lV 

1 2lVGS 
GS I  I
I
I
D2 D1
1 lVGS  O REF 1 lVGS 
2 Microelettronica – Circuiti integrati analogici 2/ed
Richard C. Jaeger, Travis N. Blalock
v gs r  v
1
m3

 o3
i
vgs  v  v  x  (m v )
2 1 g
f2 1
m1 



vx
1

Rout 
 r  m  2  m   m r
f 2 o3
i x o3 f 2
f 2 
m
V  f2
CS l
3
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Bipolar Wilson Current Source
I I
O REF
1 (VBE /VA)
2V
1 

2
BE

 b ( b  2) V 
 FO FO
A 
Addition of extra BJT can balance the
circuit and reduce errors due to mismatch.
During operation, all transistors are
in active region. But some current is
lost at base of Q3 and current gain
error is formed by Q1 and Q2.
IREF = IC2 + IB3
VCE1 = VBE
VCE2 = VBE+VBE3 -VBE4
= VBE
b r
VCE2 = 2VBE
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Richard C. Jaeger, Travis N. Blalock
Rout  o3 o3
2
V 
CS
boV
A
2
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MOS Cascode Current Source
ID1 = ID3 = IREF Also IO = ID4 = ID2. So current
mirror forces output current to be approximately
equal to the reference current. If all transistors are
matched with equal W/L ratios,
VDS2 = VGS1+ VGS3 -VGS4 = VGS = VDS1
From the small-signal model,
Rout  r 1 g r   m r
o4 
m4 o2 
f 4 o2
m
V
CS
m
 f4 f4
l
2
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Richard C. Jaeger, Travis N. Blalock
l
4
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Bipolar Cascode Current Source
IC1 = IC3 = IREF Also IO = IC4 = IC2. So current
mirror forces output current to be approximately
equal to the reference current. If all transistors are
matched,
VCE2 = VBE1+ VBE3 -VBE4 = VGS = VCE1
From the small-signal model,
b r
Rout  o4 o4
2
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Richard C. Jaeger, Travis N. Blalock
b V
V  o4 A4
CS
2
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Electronic Current Source Design
Example
Problem: Design IC current source to meet given specifications.
Given data: IREF = 25 mA, VSS = 20 V, l = 0.02 V-1 , VTN = 0.75 V, Kn’ = 50
mA/V2, VA = 50 V, bFO = 100, ISO = 0.5 fA
Analysis: MR <0.1 % requires output current of 25 mA±25 nA when output
voltage is 20 V.
Choose 1GW for safety margin.
20V
Rout 
 800MW
25nA
V
 25mA(1GW)  25,000V
CS
Cascode or Wilson source’s voltage-balanced MOS version must be used to
meet this value of VCS and for small MR. We can choose cascode source as
it doesn’t involve internal feedback loop.W/L ratios are all same as MR=1.
1
m  lV  0.02  25,000V   500  gmro  2Kn I
D lI
CS V
f
D
Using mf =500, l =0.02/V and ID =25 mA gives value of Kn=1.25 mS. Since Kn
= Kn’(W/L) we need a W/L ratio of 25/1 for given technology.
2 Microelettronica – Circuiti integrati analogici 2/ed
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Reference Current Generation
• Reference current is required by all current mirrors.
• When resistor is used, source’s output current is directly
proportional to VEE.
V
V
EE
BE
I

REF
R
• Gate-source voltages of MOSFETs can be large and
several MOS devices can be connected in series between
supplies to eliminate large resistors.
VDD + VSS = VSG4+ VGS3 + VGS1 and ID3 = ID1 = I4
• Change in supply directly alters gate-source voltage of
MOSFETs and the reference current.
• BJTs can’t similarly be connected in series due to small
fixed voltage developed across each diode and
exponential relation between voltage and current.
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Richard C. Jaeger, Travis N. Blalock
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Supply-Independent Biasing: JFET
Constant Reference Current Source
• P-channel JFETs can be used to
set a fixed reference current.
• JFET is operating with VSG=0 and
thus ID= IDSS, assuming that VSD is
large enough to pinch-off the
JFET.
• Depletion-mode MOSFETs can be
used in similar manner.
• Since both these methods require
special IC processes, other
methods are preferred.
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Richard C. Jaeger, Travis N. Blalock
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Supply-Independent Biasing: VBE -based
Reference and Widlar Current Source







•

 V
V
BE1  I   BE1  0.7V
I  I 
O F 2 E2 F 2 R
B1  R2
R

2
2

V 1.4V
V
T
I  ln EE
O R
I R
2
S1 1
Output current is now logarithmically
dependent on supply voltage. However, it is
Output current is determinedtemperature dependent due to temperature
by base-emitter voltage of coefficients of both VBE and R.
Q . For high current gain, Widlar source also achieves similar supply
V 1 V
V
V
1.4V
independence of output current.
EE
BE
1
BE
2
EE
I 


C1
I
A 
V
R
R
1
1
I  I
 T ln REF E 2 
F E2 R  I
O
A 

O
E1 

2 Microelettronica – Circuiti integrati analogici 2/ed
Richard C. Jaeger, Travis N. Blalock
Copyright © 2005 – The McGraw-Hill Companies srl
Supply-Independent Biasing: Bias Cell
Using Widlar Source
and
Current
Mirror
Actual value of output current depends on temperature
and absolute value of R. IC1 = IC2 =0 is also a stable
operating point and start-up circuits must be included
in IC realizations to ensure that circuit reaches desires
operating point.
Base-emitter voltages of Q1 and Q4 can be used as
reference voltages for other current mirrors.
Assuming high current gain, pnp In MOS analog of the circuit, I = I and so
D3
D4
current mirror forces IC1 = IC2.
ID1 = ID2.
Emitter area ratio for Widlar

source is shown to be 20.

(W / L) 
V
0.0749V
I  T ln 20 
C1 R
R
2 Microelettronica – Circuiti integrati analogici 2/ed
Richard C. Jaeger, Travis N. Blalock
R
2
1
1
I K 
(W / L) 
D2 n1 
2
Copyright © 2005 – The McGraw-Hill Companies srl
Variation of Reference Cell Current with
Power Supply Fluctuations
v  V
 V
v  V
x
CC
EE or
x
ix  ( g  g ' ) v  g ' v
m1 m2 1 o2 2
DD
 V
SS
Using i  g (vx  v )
m4
2
(ng  g )vx  ( g  g )vx  ng v
m4 o3
m1 o3
m4 2
g vx  g ' v  ( g  g ' )v
m4
m2 1
m4 o2 2
Determinant of these nodal equations is:
3

2
gm 
m
2


  g g 1- n
O

m1 m4
g 
m 
F 
m1 






g
' 






R is absorbed into transistor model in
simplified small-signal circuit model.
2 Microelettronica – Circuiti integrati analogici 2/ed
Richard C. Jaeger, Travis N. Blalock
Copyright © 2005 – The McGraw-Hill Companies srl
Variation of Reference Cell Current with
Power Supply Fluctuations (contd.)









 
g g v
v  g ( g  ng ' )  O  m o   x
1
m4 m3
o2
 m  
 f  
























r
r ' 
g '

o3
o2 1 n m2 
Rout 

g ' 1 n 
ix
g 
m
2
m1 
1

g
m1
vx












g '
2  v
g
v  g g 1 n m2   O  m   x
2
m1 m4 
g   m  
m1   f  

g
'
m
2
n
1
for g
.This is important
m1
for stability. Because of positive
feedback, overall output resistance
is reduced.
Output resistances of the Widlar source and current mirror, ro2’ and ro3
determine sensitivity to power supply variations. To improve output resistance
of Widlar portion , cascode sources can be used and Wilson sources can be
used to improve output resistance of current mirror.
2 Microelettronica – Circuiti integrati analogici 2/ed
Richard C. Jaeger, Travis N. Blalock
Copyright © 2005 – The McGraw-Hill Companies srl
Reference Current Design Example
Problem: Design supply-independent current source to meet given
specifications.
Given data: output current = 45 mA,T=300 K, total current< 60 mA VCC =
VEE= 5 V, VA = 75 V, bFO = 100, ISO = 0.1 fA, VT = 25.88 mV
Analysis:







A  I R  45μA 1kW 

  1.739
ln C1 E 2   C 2  
I
A 
V
25.88mV
T
C 2 E1 
I
A
C1 E 2  5.69
I
A
C 2 E1
I
I
45μA
Also IC2  15μA  3 . Choose IC2=5 IC1. Then AE2/ AE1 <28.45 Choosing
C1
AE2/AE1 =20,
25.88mVln(4) 45μA 1kW 
R
 797W
45μA
Finally, AE1=A, AE2=20 A, AE3=A, AE4=5 A with 35.88 mV across R.
2 Microelettronica – Circuiti integrati analogici 2/ed
Richard C. Jaeger, Travis N. Blalock
Copyright © 2005 – The McGraw-Hill Companies srl
Bandgap Reference
V
BG
V
BE
 GV
PTAT
To have zero temperature coefficient,
V
V
V
BG  BE  G PTAT
T
T
T
V
V
 3V
V
BE
T
GO

 G PTAT  0
T
T
GV
V
 3V V
T
BE
PTAT
GO
To make the voltage reference
temperature independent,
negative temperature coefficient
of base-emitter junction can be
VGO is silicon bandgap voltage at 0K (1.12
canceled by positive
V
V
 3V
temperature coefficient of V)
T
BG
GO
scaled PTAT voltage.
2 Microelettronica – Circuiti integrati analogici 2/ed
Richard C. Jaeger, Travis N. Blalock
Copyright © 2005 – The McGraw-Hill Companies srl
Bandgap Reference Circuit Realization
V
BE1 V
 3V V
R
T BE
GO
2   1 T

R
2 VPTAT
2V
1
PTAT
T
Voltages other than
1.2 V can be obtained
by a adding resistive
voltage divider.
R
A
2
V
V
 2 V ln E 2
BG
BE1
R T A
1
E1







R 
V  1 4 V
O
R  BG
3
Circuit gain G =2 R2 / R1.
2 Microelettronica – Circuiti integrati analogici 2/ed
Richard C. Jaeger, Travis N. Blalock
Copyright © 2005 – The McGraw-Hill Companies srl
Bandgap Reference Example
Problem: Design bandgap reference to meet given specifications.
Given data: VO = 5 V,T=320 K, collector current = 25 mA, IS = 0.5 fA.
Assumptions: VA is infinite, bFO is infinite, AE2 =10 AE1, drop across R =2 V.
Analysis:


I
A 
C1 E 2 
V
 kT
ln
PTAT q
I
A 
C 2 E1 
 (27.57mV)ln(10)  63.47mV
V
R  PTAT  63.47mV  2.539kW
1
I
25mA
E


I

 C1 
V
V ln
 0.6792V
BE1 T  I 


 S1 
 3V V
R V
T
BE  4.124
2  GO
R
2V
1
PTAT






2 Microelettronica – Circuiti integrati analogici 2/ed
Richard C. Jaeger, Travis N. Blalock
R  4.124R 10.47kW
2
1
R
V
V
 2 2V
 1.203V
BG
BE1
PTAT
R
1
V
R
4  O 1  3.157
R V
3
BG
V V
V
BG  75.9kΩ
BG
R 
 24kΩ R4  O
3
I
I
3
3
R  2V  80kW
25mA
Copyright © 2005 – The McGraw-Hill Companies srl
CMOS Differential Amplifier with
Active Load: DC Analysis
V V
V
V

DD
DD
O
SD4
V
V
DS1
SD3
V







V
V

DD
TN
TP
V
SG3

I
SS V
TP
Kp
I
SS 
Kn







I
SS V
DD
Kp
I
SS V
TP
Kp
ID3 = ID1 = ID2 =ID4 =IDSS/2.
Mirror ratio is set by M3 and M4 and is exactly
unity when VSD4 = VSD3 and thus VSD1 = VSD2.
Differential amplifier is completely balanced at
dc when:
2 Microelettronica – Circuiti integrati analogici 2/ed
Richard C. Jaeger, Travis N. Blalock
Copyright © 2005 – The McGraw-Hill Companies srl
CMOS Differential Amplifier with Active Load:
Differential-Mode Signal Analysis
The differential amplifier can be
represented by its Norton equivalent.
Total short circuit output current:
g
v
io  2 m2 id  g v
m2 id
2
2 Microelettronica – Circuiti integrati analogici 2/ed
Richard C. Jaeger, Travis N. Blalock
Thevenin equivalent output resistance:
R r r
th o2 o4
Differential-mode voltage gain:








m
A  iscR  g
r r  f2
dm
th m2 o2 o4
2
Copyright © 2005 – The McGraw-Hill Companies srl
CMOS Differential Amplifier with
Active Load: Output Resistance
Drain current of M2 (vx/2ro2)is replicated by
current mirror as drain current of M4. Total
current from source is 2(vx/2ro2)= vx/ro2.
Total current is:
vx vx
T

ix 
r
r
o2 o4
Output resistance is:
Assume RSS >>1/ gm1.
R r r
od o2 o4
Resistance looking into drain of
M2 (C-G transistor) is: 






R  r 1 g R   r 1 g
o2 o2 
m2 S  o2
m2 g
2 Microelettronica – Circuiti integrati analogici 2/ed
Richard C. Jaeger, Travis N. Blalock
1
m1







 2r
o2
Copyright © 2005 – The McGraw-Hill Companies srl
CMOS Differential Amplifier with Active
Load: Common-Mode Signal Analysis
From small-signal equivalent:
v
R  2r
o2
od
ioc  ic
Roc  2m R
2Rss
f SS
 ioc
v 
3 g  g   g / 2   G
m3 o3  o2  oc  r 

o3 
1


  v
r

g






o
2

ic 
isc  ioc  g v  o2 v    

m4 3 2 3 

 2R

m


f 3  SS 
where it is assumed that gm4 = gm3 and Goc << gm3.


r 

Also
o3 
1

r  
isc R

o2   r r 
th   
Acm 
v
2m R  o2 o4 
ic
f 3 SS
2 Microelettronica – Circuiti integrati analogici 2/ed
Richard C. Jaeger, Travis N. Blalock
Copyright © 2005 – The McGraw-Hill Companies srl
CMOS Differential Amplifier with Active Load:
CMRR and Mismatch Contribution
2m g R
A
f 3 m2 SS  m g R
CMRR  dm 
for ro3 = ro2.


m
2
SS
f
3
Acm
1  r / r 
With mismatched transistors, assuming
 o3 o2 
vd1=0 and gate-source voltages are equal,
isc  i  i  gmvgs  govs
d1 d 2
With vgs= vic- vs, vd1=0 and vd2=0,
2 gm R
SS v  v
vs 
ic ic
1 2 g m R
SS




1 2 go R

1
1 
SS v  
vgs 

v
ic

 ic
1 2 g m R
m 
 2 g m R
SS
SS
f 






A
A

g

 go 1
1
1

cm
CMRR-1  cm 
 m 




A
gm  2 gm R
m  go m
gm r r

SS
dm
f 
f
o2 o4 


2 Microelettronica – Circuiti integrati analogici 2/ed
Richard C. Jaeger, Travis N. Blalock







Copyright © 2005 – The McGraw-Hill Companies srl
Bipolar Differential Amplifier with
Active Load: DC Analysis
Differential amplifier is completely balanced at dc when:
V V
V
EB
O
CC
V
V
V V  (V
V )  (V
) V
E
EB
BE
CE1 CE2 C
CC
CC
Current gain defect in current mirror upsets dc balance.
As longs as BJTs are in forward-active region, VEC4
adjusts to make up for current-gain defect.
I
I
C4 C1
1 (VCE4 /VA)
1 VCE  2  As IC2 =IC4 and IC2
 V
 =IC1, MR must be
b

A
FO4 
1./2.
IC3 = IC1 = IC2 =IC4 =IEE
2V
A This causes an equivalent
If bFO is very large, current
V
V

EB
EC4
b
FO4 input offset voltage of
mirror ratio is set by Q3 and
V
V
V
V
Q4 and is exactly 1 when VEC4 V  EC4 EC3  EC4 EB
OS
A
A
= VEC3=VEB.
dd
dd
2 Microelettronica – Circuiti integrati analogici 2/ed
Richard C. Jaeger, Travis N. Blalock
Copyright © 2005 – The McGraw-Hill Companies srl
Bipolar Differential Amplifier with Active
Load: Differential-Mode Signal Analysis
Thevenin equivalent
output resistance:
R r r
th o2 o4
Differential-mode voltage gain:
isc R R
L th  g  r r R   g R
A 
m2 o2 o4 L  m2 L
dm
v
dm
With added stages,
output resistance of
To eliminate offset error, buffered
differential input
current mirror active load is used.
stage is:
Total short circuit output current:
Req  r r r  r
g v
o2 o4  5  5
m
2
id
isc  2
g v
m2 id
A  g Req
2
m2
dm
b I /I
o5 C 2 C5

2 Microelettronica – Circuiti integrati analogici 2/ed
Richard C. Jaeger, Travis N. Blalock

Copyright © 2005 – The McGraw-Hill Companies srl
Bipolar Differential Amplifier with Active
Load: Common-Mode Signal Analysis
Current forced in differential output resistance
is doubled due to current mirror action.



v 
 1


1
1
1
1
isc  2v 

 ic 



ic boro 2R  g (2r ) m  boro 2R 
EE  m3 o2
EE 

f2 
1





g R
 2 
 
1
1
m
2
th

CMRR 




isc R / v
b
m
2
g
R
b
m2 EE  
th ic  o3  o f 2
From small-signal equivalent:
Due to mismatches,


Acc v




1
1


ic




ioc 
v 


 g


g

g

1
1
1


ic
2
R
1


m

o
b
ro


CMRR




R


o
EE




 g
C
g  2 gm R
m  go m 

m


SS
f 
f 



2  1
1
isc  v



ic b  boro 2R 
EE 
o
2 Microelettronica – Circuiti integrati analogici 2/ed
Richard C. Jaeger, Travis N. Blalock
Copyright © 2005 – The McGraw-Hill Companies srl
Active Loads in Op Amps: Voltage Gain
va v b v o
A 
 A A (1)  A A
vt1 vt 2
vt1 vt 2
dm v v v
id a b
m
m
A  g (r r )  f 2
vt1 m2 o2 o4
2
m
 f2 f5
4
If Wilson stage is used in first-stage active
load, Avt1 = mf2. If current source M10 is
replaced by a Wilson or cascode source,
Avt2 = mf5.Overall gain can be raised to:
m
A m m
dm
f2 f5
A  g (r ( R
 r ))  g (r r )  f 5
vt2 m5 o5 GG o10
m2 o2 o5
2
Gain of output stage is approximately 1.
2 Microelettronica – Circuiti integrati analogici 2/ed
Richard C. Jaeger, Travis N. Blalock
Copyright © 2005 – The McGraw-Hill Companies srl
Active Loads in Op Amps: DC Design
Considerations
• When op amp with active load is
operated in closed-loop
configuration, ID5 = I2, the
output current of source M10.
• For minimum offset voltage,
(W/L)5 must be such that VSG5 =
VSD4 = VSG3 precisely sets ID5 =
I2 and accounts for VDS and l
differences between M5 and M10.
• RGG, (W/L)6 and (W/L)7
determine quiescent current in
class-AB output stage.
• VGS11 can be used to bias output
stage in place of RGG.
2 Microelettronica – Circuiti integrati analogici 2/ed
Richard C. Jaeger, Travis N. Blalock
Copyright © 2005 – The McGraw-Hill Companies srl
CMOS Op Amp Analysis
Problem: Find small-signal characteristics of given CMOS op amp.
Given data: IREF = 100 mA, VDD = VSS = 5 V, VTN = 1 V, VTP = -0.75 V,
Kn‘ = 25 mA/V2, Kp‘ = 10 mA/V2, l = 0.0125 V-1
2I
Analysis:
D11  2.54V
V
V

I
 I /2  I
100μA
GS11 TN11
K
n11
REF
D2 1
As ID6 = ID7, VGS6 = VSG7 = VGS11 /2
I
 I  2I
 200μA
D5 2
REF
250 μA
m m
I
I

(1.27V  0.75V)2
D7 D6
2 V2
A  f2 f5
dm
4
 33.7μA


2K 


2
K
g  g 1.310 4S

1 1
 1
p
5
n
2
m7
m6
 
  16,000



 l
4  l
I
I
 5

D5 
D 2 
1
1
 2
Rout 
 3.85kW
g
g
R  R 
m6 m7
id ic
2 Microelettronica – Circuiti integrati analogici 2/ed
Richard C. Jaeger, Travis N. Blalock
Copyright © 2005 – The McGraw-Hill Companies srl
Bipolar Op Amps
•
Load resistance is driven by
class-AB output stage formed
by Q6 and Q7 , biased by I2 and
diodes Q11 and Q12.
A A A A
dm vt1 vt 2 vt3
  g









r r ( b 1)R  (1)
L  
m2 o5 o8 o6
 m2  5
m
g
I
r
f5
o5  C 2 b
 m2 g r g
m5  5 m5 2 I
o5 2
• Q1 to Q4 form differential input gm5
C5
r
g
stage with active load.
• First stage is followed by highgain C-E amplifier, Q5 and its
current source load, Q8.
2 Microelettronica – Circuiti integrati analogici 2/ed
Richard C. Jaeger, Travis N. Blalock
Copyright © 2005 – The McGraw-Hill Companies srl
Bipolar Op Amps with Improved
Voltage Gain
Buffered current mirror maintains dc
balance at collectors of Q3 and Q4.
Using I2 =2 I1, bo=50, VA=60 V,
VCE= 15 V,
r
A  g ( o2 2b r )  0.23m
vt1 m2 2
f2
o6  7
m
g
2r
A  m7 ( o7 r )  f 7
vt 2
2
3 o14
2
To improve gain, 2-transistor Darlington circuit
with current gain of bo1bo2, amplification factor
mf2 /4, output resistance ro2 /2 and input
resistance 2bo1 r2,is used to replace Q5. It
requires emitter-base bias of 2VEB.
2 Microelettronica – Circuiti integrati analogici 2/ed
Richard C. Jaeger, Travis N. Blalock
A  A A A
dm vt1 vt2 vt3
m m
 f 2 f 7  4.15105
22
Copyright © 2005 – The McGraw-Hill Companies srl
Input Stage Breakdown in Bipolar Op
Amps
• Input stage of bipolar op amp has no
overvoltage protection and can easily
be destroyed by large input voltage
differences due to fault conditions or
unavoidable transients, such as slewrate limited recovery.
• In worst-case fault condition, B-E
junction of Q1 is forward-biased and
that of Q2 is reverse-biased by(VCC +
VEE - VBE1). If VCC = VEE =22 V, reverse
voltage > 41 V.
2 Microelettronica – Circuiti integrati analogici 2/ed
Richard C. Jaeger, Travis N. Blalock
Early IC op amps used external
diode protection across input
terminals to limit differential input
voltage to about 1.4 V at the cost of
extra components.
Copyright © 2005 – The McGraw-Hill Companies srl
mA741 Op Amp
• High gain, input resistance and
CMRR, low output resistance
and good frequency response.
• Fully protected input and output
stages and offset adjustment port.
• Input stage is a differential
amplifier with buffered current
mirror active load.
• Two stages of voltage gain
(emitter-follower driving C-E
amplifier) followed by shortcircuit protected class-AB output
stage buffered from second gain
stage by emitter follower.
2 Microelettronica – Circuiti integrati analogici 2/ed
Richard C. Jaeger, Travis N. Blalock
Copyright © 2005 – The McGraw-Hill Companies srl
mA741 Op Amp: Bias Circuitry
Assuming VO =0, VCC =15 V and neglecting drop
across R7 and R8 ,
VEC23 = 15+1.4=16.4 V and VEC24 = 15-0.7 =14.3 V
Given VA=60 V, bFO =50,
1 (16.4 / 60)
I  0.75(0.733mA)
 666mA
2
1 (0.7 / 60)  (2 / 50)
1 (14.4 / 60)
I  0.25(0.733mA)
 216mA
3
1 (0.7 / 60)  (2 / 50)
V
V
60V 16.4V
V
V
 2V
A
23
EC
23
R


 115kW
EE
BE  0.733mA
I
 CC
2
I
0
.
666
mA
REF
R
2

 Solving iteratively,
5
I

V
V
V
 REF 
T
I 
ln
A
24
EC24  60V 14.3V  344kW

R

1 5000  I
 I =18.4 mA.
3


I
0.216mA
1
1


3
2 Microelettronica – Circuiti integrati analogici 2/ed
Richard C. Jaeger, Travis N. Blalock
Copyright © 2005 – The McGraw-Hill Companies srl
mA741 Op Amp:DC Analysis of Input
Stage
b
FO 2  b
I
 I

1 I

C2
F 2 E2 b
1 FO 4  B4

FO 2

I
I
 1
C2 2









1











V
V
EC
8
EB8  2  1
1
V
b
b
A8
FO8
FO 4
b
1 b
FO
2
FO 4 I
I
 I

C4
F 4 E4
b
b
1 C 2
FO2
FO 4
V
V
V
V
V
V
CE1 CE2
CC
EB9
BE2
CC
V
V V  0.7V - (-V
1.4V)
EE
EC3
E3 C3
V
 2.1V
EE
I
 I /2
C16 1
1 (V
/V )
EC
8
A8
I  2I
 2I
1
C 2 1 (2 / b
B4
)  (V
/V )
FO8
EB8 A8
2 Microelettronica – Circuiti integrati analogici 2/ed
Richard C. Jaeger, Travis N. Blalock
V
1.4V
CC
V
V
 0.7V
CE7 EE
V
EC8
Copyright © 2005 – The McGraw-Hill Companies srl
mA741 Op Amp: Input Stage Bias
Currents Example
Problem: Calculate bias currents in the 741 input stage with given parameters.
Given data: I1 = 18 mA,VCC = VEE= 15 V, VAnpn = 75 V, bFOnpn = 150, VApnp = 60
V, bFOpnp = 60
Analysis: V
V V
V
16.4V
EC8 CC BE1 EB3
18mA
1
I I 
 7.32mA
C1 C 2
1 (16.4 / 60)
1
2

1 (2 / 50)  (0.7 / 60) (150/151)(60 1)

b
I
1  b
C 2   FO 2  FO 4 I
I  I  I  I 
C6 C3 C 4
F 4 E4
F4
 b
b
1 C 2


F2

FO 2

FO 4
60  150 

 IC 2  7.25mA
61  151
I  I  7.25mA
C5 C 3

2 Microelettronica – Circuiti integrati analogici 2/ed
Richard C. Jaeger, Travis N. Blalock
Copyright © 2005 – The McGraw-Hill Companies srl
mA741 Op Amp: AC Analysis of Input
Stage
Using symmetry of the input stage differentialmode half circuit can be drawn.
io   ie   ( b 1)i  b i
o4
o4 o2
b
v /2
id
i 

b r  ( b 1)R
2
o2
in4 r
v
g
2
id  m2 v
io  b
o2 4r
4 id
2
v
R  id  4r
2
id i
b
o2 b
v
 (b
id
o2
/2







1)
r
b
4
o4
1








v
id
4r
2
Rout  r 1 g R   2r
o4
o4
m4 
2 Microelettronica – Circuiti integrati analogici 2/ed
Richard C. Jaeger, Travis N. Blalock
Copyright © 2005 – The McGraw-Hill Companies srl
mA741 Op Amp: Voltage Gain (Input
Stage)
g
v
m
2
id  20I v
io  2i  C 2 id
2
 (1.4610 4S)v
id
2 Microelettronica – Circuiti integrati analogici 2/ed
Richard C. Jaeger, Travis N. Blalock


R R
R
 r 1 g R 2r
out6 out4 o6
th
m6 2 o4
 1.3r 2r  0.79r  6.54MW
o4
o6 o4
Based on values in Norton equivalent, opencircuit voltage gain of first stage is -955.
Copyright © 2005 – The McGraw-Hill Companies srl
mA741 Op Amp: Voltage Gain (Second
Stage)
R
r
  b
1100  20.7kW
in11  11  o11 



y 
11
1



  2.4MW
  b
1 50kW R
 10  o10 
in11
r
I
V
C
11
I
I

 B11  19.8mA
C10 E10 b
50kΩ
F11
b
r
 o10  189kΩ
 10 I
C10
 5.63kΩ v  v
 11
e 1
r
To find y11 and y21:
2 Microelettronica – Circuiti integrati analogici 2/ed
Richard C. Jaeger, Travis N. Blalock
bo10 150kW Rin11  0.921v
1
r
 b
150kW R

 10
o10
in11
i 
2 (1/ g
ve
 0.006701v
1
) 100W
m11
y  6.70mS
21
Copyright © 2005 – The McGraw-Hill Companies srl
mA741 Op Amp: Voltage Gain (Second
Stage contd.)
To find y12 and y22:
R
 r 1 g
R 100  407kW
out11 o11
m11 E 



y
22



1





  89.1kW
R R
2 out11
Open-circuit voltage gain for the first two
stages is:
v  0.00670(89.1kW)v  597v
2
1
1
v  1.4610 4  6.54MW 2.4MW v  256v
1
id
id
v  597(256v )  153,000v
2
id
id
2 Microelettronica – Circuiti integrati analogici 2/ed
Richard C. Jaeger, Travis N. Blalock
Combined model for first and
second stages is:
Copyright © 2005 – The McGraw-Hill Companies srl
mA741 Op Amp: Voltage Gain (Output
Stage)
From simplified output stage without
short-circuit protection:
R
r
  b
1 R  304kW
eq2  15  o15  L
R
r
r
R R
 162kW
eq1 d14 d13
3 eq2
R
r
  b
1 R
 8.27MW
in12  12  o12  eq1
2 Microelettronica – Circuiti integrati analogici 2/ed
Richard C. Jaeger, Travis N. Blalock







r
y
1 
22
R
R r
r
  12
eq3
3 d14 d13
b
1
o12
 2.08kW
r
R

15
eq3  26.2W
Ro 
b
1
o15
Actual op amp output resistance is:
Rout  Ro  R  53W
7
Copyright © 2005 – The McGraw-Hill Companies srl





Gilbert Analog Multiplier
vo   (i  i )  (i
 i )  R
C5
C 4 C6 
 C3
  (i  i )  (i  i )  R
C4
C5 C 6 
 C3




 v
v 

R


 (i  i ) R tanh 2   v   tanh 2
C1 C 2
2V  1 R 
 2V
T
T



 1










Multiplication can be achieved by expanding
the tanh as a series and keeping only first
term.


3


 v



x
 R 
tanh(x)  x   ... vo  v   tanh 2 
1 R 
 2V 
2
T
Q1 and Q2 have significant emitter



 1
degeneration, transconductance of
the pair is 1/ R1.For v1 < R1IBB, But this restricts input signal range of v2 to
only a few tens of mV.
2 Microelettronica – Circuiti integrati analogici 2/ed
Richard C. Jaeger, Travis N. Blalock
Copyright © 2005 – The McGraw-Hill Companies srl
Four-Quadrant Gilbert Analog
Multiplier withv Predistortion
Circuit
 (V  v
)  (V  v
)v
v
BE10
v




3
1









i

i

I
R

 C7 
 C8 
EE 3 
V tanh
 V tanh
  V tanh
v
T
T
T


 I

 I

3






1

 S 
 S 

I R 

EE 3 





v



1
3
 2V tanh 

T
I

R


 EE 3 
2
For v3 < R3IEE,
v
EE
i 
 3
C7
2 2R
3
v
I
i  EE  3
C8
2 2R
3
I
vo 
2 Microelettronica – Circuiti integrati analogici 2/ed
Richard C. Jaeger, Travis N. Blalock
BB







BE10
BB
BE9
BE9







R
vv
I RR 13
EE 1 3
Copyright © 2005 – The McGraw-Hill Companies srl